Memory with refresh cycle donation to accommodate low-retention-storage rows
AssigneeRambus Inc.
InventorsScott C. Best, Ely K. Tsern
Life of this patent
Estimating the term…
Abstract
In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated with a low-retention row of storage cells once every nth refresh interval.
Claims32
A method of operation within a dynamic random access memory (DRAM) device having a plurality of rows of storage cells including high-retention rows that exhibit retention times equal to or longer than a first time interval, normal-retention rows that exhibit retention times less than the first time interval but greater than or equal to a second time interval and one or more low-retention rows that exhibit retention times less than the second time interval, the method comprising:
- refreshing each normal-retention row exactly once per refresh interval;
- refreshing each low-retention row more than once per refresh interval;
- refreshing each high-retention row that is associated with a low-retention row once every X refresh intervals, where X is an integer greater than one;
- and
- wherein the same total number of refresh operations is executed in each refresh interval.
A dynamic random access memory (DRAM) device comprising:
- a plurality of rows of storage cells including high-retention rows that exhibit retention times equal to or longer than a first time interval, normal-retention rows that exhibit retention times less than the first time interval but greater than or equal to a second time interval and one or more low-retention row that exhibit a retention time less than the second time interval;
- a refresh counter to generate a repeating sequence of count values during each refresh interval, tREF, each count value including an address component;
- lookup table circuitry to receive each count value from the refresh counter and to output a replacement address and activate a match line if the count value matches an entry stored within the lookup table circuitry;
- and
- circuitry to perform, during each refresh interval, a sequence of refresh operations at storage rows indicated by respective address components of the sequence of count values, skipping, until a subsequent refresh interval, a refresh operation at any storage row for which the match line is activated by the lookup table circuitry, and refreshing a row indicated by the replacement address instead, wherein the lookup table circuitry comprises a lookup table storage to store, for each of the low-retention rows, an address of the low-retention row, addresses of two or more high-retention rows that have been selected to donate refresh cycles to the low-retention row, and one or more midpoint addresses having selected offsets from the address of the low-retention row.
Computer-readable storage media comprising a computer-executable netlist of a dynamic random access memory (DRAM) device circuit, the netlist having instructions and data for forming an integrated circuit, including instructions and data for forming:
- a plurality of rows of storage cells;
- a refresh counter to generate a sequence of count values during each refresh interval, each count value including an address component;
- lookup table circuitry to receive each count value from the refresh counter and to output a replacement address and activate a match line if the count value matches an entry stored within the lookup table circuitry;
- and
- circuitry to perform, during each refresh interval, a sequence of refresh operations at storage rows indicated by respective address components of the sequence of count values, skipping, until a subsequent refresh interval, a refresh operation at any storage row for which the match line is activated by the lookup table circuitry, and refreshing a row indicated by the replacement address instead, wherein the lookup table circuitry comprises a lookup table storage to store the addresses of one or more low-retention rows that exhibit retention times less than a first time interval, and for each low-retention row, addresses of two or more high-retention rows that exhibit retention times equal to or longer than a second time interval and that have been selected to donate refresh cycles to the low-retention row, and one or more midpoint addresses having selected offsets from the address of the low-retention row.
A dynamic random access memory (DRAM) device comprising:
- a plurality of rows of storage cells including high-retention rows that exhibit retention times equal to or longer than a first time interval, normal-retention rows that exhibit retention times less than the first time interval but greater than or equal to a second time interval, and a low-retention row that exhibits a retention time less than the second time interval;
- means for refreshing each normal-retention row exactly once per refresh interval;
- means for refreshing the low-retention row X times per refresh interval;
- means for refreshing each of the high-retention rows that is associated with a low-retention row once every X refresh intervals, X being an integer greater than one;
- and
- wherein the same total number of refresh operations is executed in each refresh interval.
A dynamic random access memory (DRAM) device comprising:
- a plurality of rows of storage cells including high-retention rows that exhibit retention times equal to or longer than a first time interval, normal-retention rows that exhibit retention times less than the first time interval but greater than or equal to a second time interval, and one or more low-retention rows that exhibit retention times less than the second time interval;
- and
- refresh circuitry to refresh each normal-retention row exactly once per refresh interval, refresh each low-retention row X times per refresh interval, and refresh each high-retention row that is associated with a low-retention row once every X refresh intervals, X being an integer greater than one, and wherein the same total number of refresh operations is executed in each refresh interval.
Dependencies are inferred from the claim text.