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US 7,564,309 B2Granted
Wide input common mode for input bias current cancellation
AssigneeNational Semiconductor Corporation
InventorKwok-Fu Chiu
Life of this patent
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Abstract
Described herein is technology for, among other things, input bias current cancellation. The technology includes a bipolar differential pair coupled with a supply voltage (VCC). The bipolar differential pair includes a first transistor and a second transistor. The technology further includes an input bias current cancellation circuit coupled with the bipolar differential pair and including a third transistor. The third transistor has a collector-emitter voltage VCE, and the bipolar differential pair is operable to receive an input voltage greater than VCC−2VCE without causing the third transistor to operate in the saturation region.
Claims20
A circuit, comprising:
- a bipolar differential pair coupled with a supply voltage (VCC) and comprising a first transistor and a second transistor wherein collector currents of said first and second transistor are not required to be equal to collector currents of other transistors in said circuit;
- and
- an input bias current cancellation circuit coupled with said bipolar differential pair and comprising a third transistor, wherein said third transistor has a collector-emitter voltage VCE, wherein further said bipolar differential pair is operable to receive an input voltage greater than VCC−2VCE without causing said third transistor to operate in the saturation region, and wherein said input bias current cancellation circuit further comprises:
- a current source for generating a first current that is proportional to a second current, wherein said second current drives said bipolar differential pair;
- a fourth transistor coupled with said current source, wherein said current source drives said first transistor;
- a base current sensing circuit coupled with said fourth transistor and for sensing a base current of said fourth transistor;
- and
- a current mirror coupled with said base current sensing circuit and said bipolar differential pair, said current mirror for mirroring said base current of said fourth transistor to bases of said bipolar differential pair.
5 more elements
A circuit, comprising:
- a bipolar differential pair coupled with a supply voltage (VCC) and comprising a first transistor and a second transistor wherein collector currents of said first and second transistor are not required to be equal to collector currents of other transistors in said circuit;
- and
- a input bias current cancellation circuit coupled with said bipolar differential pair and comprising a third transistor, wherein said third transistor has a collector-emitter voltage VCE, wherein further said bipolar differential pair is operable to receive an input voltage up to VCC−VCE without causing said third transistor to operate in the saturation region, and wherein said input bias current cancellation circuit comprises:
- a current source for generating a first current that is proportional to a second current, wherein said second current drives said bipolar differential pair;
- a fourth transistor coupled with said current source, wherein said current source drives said fourth transistor;
- a base current sensing circuit coupled with said fourth transistor and for sensing a base current of said fourth transistor;
- and
- a current mirror coupled with said base current sensing circuit and said bipolar differential pair, said current mirror for mirroring said base current of said fourth transistor to bases of said bipolar differential pair.
5 more elements
A circuit for canceling input bias current for a bipolar differential pair, wherein said bipolar differential pair is driven by a first current generated by a first current source, said circuit comprising:
- a second current source for generating a second current that is proportional to said first current;
- a first transistor coupled with said second current source, wherein said second current source drives said first transistor;
- a base current sensing circuit coupled with said first transistor and for sensing a base current of said first transistor;
- and
- a current mirror coupled with said base current sensing circuit and said bipolar differential pair, said current mirror for mirroring said base current of said first transistor to bases of said bipolar differential pair, wherein said differential pair is operable to receive an input voltage greater than VCC−2VCE without causing transistors of said current mirror to operate in their respective saturation regions and wherein collector currents of transistors of said bipolar differential pair are not required to be equal to collector currents of transistors that are a part of said circuit for canceling input bias.
2 more elements
A method for canceling input bias current for a bipolar differential pair, comprising:
- generating a second current that is proportional to a first current, wherein said first current drives said bipolar differential pair;
- biasing a transistor with said second current;
- and
- mirroring a base current of said transistor for bases of said bipolar differential pair, wherein said bipolar differential pair is operable to receive an input voltage rater than VCC−2VCE without causing at least one transistor used for the mirroring the base current of said transistor to operate in a saturation region and wherein collector currents of transistors of said bipolar differential pair are not required to be equal to collector currents of other transistors.
1 more element
Dependencies are inferred from the claim text.