Logic state catching circuits

A method for catching a logic state comprising:

• resetting a latching element of a logic state catching circuit during a predefined period;
• driving within one stage of logic a change in state of a data-in signal on an output of the logic state catching circuit;
• latching the latching element to the logic state of the data-in signal in response to the change in state of the data-in signal;
• using an output of the latching element to hold the output state of the output of the logic state catching circuit;
• and
• holding the latched logic state of the data-in signal until a clock transitions to a state that holds the latching element in a reset state.

A logic state catching circuit comprising:

• a logic circuit with a first input, a second input, and an output, the logic circuit configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output, the second input receiving a latched version of the data value to hold the representative value on the output after the data value has returned to its original state;
• a latching element configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input;
• and
• a reset element configured to hold the latching element in a reset state until a clock changes state allowing the latching element to respond to the change in state of the data value.