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US 7,564,115 B2Granted
Tapered through-silicon via structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Shien Chen, Chen-Cheng Kuo, Kai-Ming Ching, Chih-Hua Chen
Life of this patent
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Abstract
An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.
Claims15
An integrated circuit structure comprising:
- a substrate;
- a through-silicon via (TSV) in the substrate, wherein the TSV extends from a top surface to a bottom surface of the substrate, and wherein the top surface and the bottom surface are opposite surfaces of the substrate;
- a hard mask region extending from the top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV;
- dielectric layers over the substrate;
- and
- a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.
3 more elements
An integrated circuit structure comprising:
- a substrate;
- a shallow trench isolation (STI) region extending from a top surface of the substrate into the substrate, the STI region forming a ring;
- a polysilicon ring on the STI region;
- low-k dielectric layers over the substrate and the polysilicon ring;
- and
- a conductive feature extending from a top surface of the low-k dielectric layers into the substrate, wherein the conductive feature comprises a first portion in the low-k dielectric layers, and a second portion penetrating through the polysilicon ring and the ring of the STI region.
3 more elements
Dependencies are inferred from the claim text.