Chip scale power LDMOS device

A semiconductor device, comprising:

• a plurality of quasi-lateral LDMOS transistors in an up-source or drain configuration formed over a semiconductor substrate, wherein current flows across the quasi-lateral LDMOS transistors through the substrate to vertical contacts;
• a first conductive layer formed over the substrate, the first conductive layer providing respective source and drain contacts for the quasi-lateral LDMOS transistors, one of the source or drain contacts electrically coupled to the vertical contacts;
• a first isolation layer formed over the first conductive layer;
• a second conductive layer formed over the first isolation layer, the second conductive layer forming a plurality of adjacent source-drain bus pairs, each source drain bus pair comprising respective source and drain busses, wherein individual ones of the source-drain bus pairs are electrically coupled to respective source and drain contacts of a respective quasi-lateral LDMOS transistor through the first isolation layer;
• a second isolation layer formed over the second conductive layer and insulating the busses from one another;
• and
• a plurality of conductive solder bumps formed over the second isolation layer in a grid, the bumps alternatingly and directly contacted to source and drain busses through the second isolation layer, wherein at least some of the conductive solder bumps overlap both the source and drain busses of a respective source-drain bus pair so as to allow connection by an individual conductive solder bump through the second isolation layer to either a source bus or a drain bus of the respective source-drain bus pair.

A semiconductor device, comprising:

• a plurality of quasi-lateral LDMOS transistors in an up-source or drain configuration formed over a semiconductor substrate;
• a first conductive layer formed over the substrate, the first conductive layer providing respective source and drain contacts for the quasi-lateral LDMOS transistors;
• a first isolation layer formed over the first conductive layer;
• a second conductive layer formed over the first isolation layer, the second conductive layer forming a plurality of adjacent source-drain bus pairs, each source drain bus pair comprising respective source and drain busses, wherein individual ones of the source-drain bus pairs are electrically coupled to respective source and drain contacts of a respective quasi-lateral LDMOS transistor through the first isolation layer, said second conductive layer having a thickness greater than the thickness of the first conductive layer;
• a second isolation layer formed over the second conductive layer and insulating the busses from one another;
• and
• a plurality of conductive solder bumps formed over the second isolation layer in a grid, the bumps directly contacted to source and drain busses through the second isolation layer, wherein each source-drain bus pair has a plurality of said conductive solder bumps formed thereover with each of said conductive solder bumps overlapping both source and drain busses of a given source-drain bus pair so as to allow direct connection by an individual conductive solder bump through the second isolation layer to either a source bus or a drain bus of the given source-drain bus pair.