Memory mapped register file and method for accessing the same
AssigneeMarvell International Ltd.
InventorsHong-Yi Chen, Henry Hin Kwong Fan
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Abstract
A data processing system comprises a processor to process instructions. A plurality of pipeline stages to execute instructions including a register file. The register file includes a memory unit having a plurality of memory locations, each memory location being addressable by an encoded address. The encoded address corresponds to at least one register and processing mode. Input ports receive inputs for addressing at least one of the memory locations using an encoded address. Output ports to output data from at least one of the memory locations using an encoded address.
Claims20
A data processing system comprising:
- a processor to process instructions, the processor including:
- a plurality of pipeline stages to execute instructions, the plurality of pipeline stages including a register file, the register file including:
- a memory unit having a plurality of memory locations, each memory location being addressable by an encoded address, wherein the encoded address corresponds to one specific register and processor mode, wherein a plurality of registers correspond to the plurality of memory locations;
- input ports to receive inputs for addressing at least one of the memory locations using an encoded address;
- output ports to output data from at least one of the memory locations using an encoded address;
- and
- a plurality of encoders that each provide an encoded address to a respective one of the input ports, wherein each of the input ports is independently associated with a different one of the plurality of encoders.
A data processing system comprising:
- processing means for processing instructions including:
- pipeline means for executing instructions, the pipeline means including a register file means, the register file means including:
- memory means having a plurality of memory locations, each memory location being addressable by an encoded address, wherein the encoded address corresponds to one specific register means and processor mode, wherein a plurality of register means correspond to the plurality of memory locations of the memory means;
- input means to receive inputs for addressing at least one of the memory locations using an encoded address;
- output means to output data from at least one of the memory locations using an encoded address;
- and
- a plurality of encoder means for providing encoded addresses to respective ones of the input means, wherein each of the input means is independently associated with a different one of the plurality of encoder means.
Dependencies are inferred from the claim text.