Selective replication of data structures

A low-latency memory management controller comprising:

• a first memory interface configured to access a low-latency memory, the low-latency memory including a plurality of memory banks;
• a main memory interface adapted to access a main memory;
• instruction unit coupled to the main memory interface receiving a request to store a selectable number of replications of a data structure in more than one memory bank of the plurality of memory banks, the request to store a selectable number of replications including a replication factor indicative of the number of replications selected, the replication factor being any number between one and the plurality of memory banks;
• plurality of thread engines coupled to the instruction unit, each thread engine adapted for association with a selectable respective one of the plurality of memory banks;
• and
• a low-latency memory controller coupled to the instruction unit, and coupled between the first memory interface and the plurality of thread engines, the low-latency memory controller storing each of the selected number of replications of the data structure on a respective one of the plurality of memory banks.

A low-latency memory access system comprising:

• a plurality of memory banks;
• means for receiving a request to store a determined number of replications of a data structure in the plurality of memory banks, the request including a replication factor indicative of the number of replications selected, the replication factor being any number between one and the plurality of memory banks;
• and
• means for storing, responsive to the store request, each of the determined number of replications in a respective one of the plurality of memory banks.