# US 7,558,900 B2 · Serial flash semiconductor memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,558,900 B2 - Document ID: US7558900B2 - Status: Granted - Kind: B2 - Application number: 11/078,205 - Filed: 2005-03-11 - Published: 2006-03-30 - Granted: 2009-07-07 - Earliest claimed: 2004-09-27 - Assignees: Winbound Electronics Corp. - Inventors: Robin J. Jigour; Eungjoon Park; Joo Weon Park; Jong Seuk Lee - Web page: https://patentgrep.com/patent/US7558900B2 ## CPC - G11C 7/1045: {Read-write mode select circuits} - G11C 8/04: using a sequential addressing device, e.g. shift register, counter - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2207/108: Wide data ports - G11C 2216/30: Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories. ## Claims ### Claim 1 A flash memory comprising: a flash memory array; and an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol; wherein a first one of the pins is configurable with the interface circuit for single-bit serial transfer in compliance with the single-bit serial protocol; and wherein the first pin and a second one of the pins are configurable with the interface circuit for multiple-bit serial transfer that is addressable but unassociated with dedicated address pins in compliance with the multiple-bit serial protocol. ### Claim 2 (depends on 1) The flash memory of claim 1 wherein the single-bit serial protocol is Inter IC protocol. ### Claim 3 (depends on 1) The flash memory of claim 1 wherein the single-bit serial protocol is Serial Peripheral Interface protocol. ### Claim 4 (depends on 1) The flash memory of claim 1 wherein the multiple-bit serial protocol specifies concurrent transfer of two bits. ### Claim 5 (depends on 1) The flash memory of claim 1 wherein: a third one of the pins and a fourth one of the pins are configurable for multiple-bit serial transfer that is addressable but unassociated with dedicated address pins in compliance with the multiple-bit serial protocol; and the multiple bit serial protocol specifies concurrent transfer of four bits. ### Claim 6 (depends on 1) The flash memory of claim 1 wherein the first and second pins are input/output pins. ### Claim 7 (depends on 1) The flash memory of claim 1 wherein: the second pin is a data output pin; and the first pin is an input/output pin. ### Claim 8 (depends on 1) The flash memory of claim 1 wherein: the first pin is an input/output pin; and the second pin is a data input pin. ### Claim 9 (depends on 1) The flash memory of claim 1 wherein: the first pin is selectively configurable with the interface circuit as an input in compliance with the single bit serial protocol and as an input that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; the second pin is selectively configurable with the interface circuit as a data output in compliance with the single bit serial protocol and as a data output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and wherein a third one of the pins is an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol. ### Claim 10 (depends on 9) The flash memory of claim 9 wherein the single-bit serial protocol is Serial Peripheral Interface. ### Claim 11 (depends on 9) The flash memory of claim 9 wherein the multiple bit serial protocol specifies concurrent transfer of two bits. ### Claim 12 (depends on 9) The flash memory device of claim 9 wherein: a fourth one of the pins and a fifth one of the pins are inputs/outputs that are addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and the multiple bit serial protocol specifies concurrent transfer of four bits. ### Claim 13 (depends on 1) The flash memory of claim 1 wherein: the first pin is selectively configurable with the interface circuit as an input/output in compliance with the single bit serial protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and the second pin is an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol. ### Claim 14 (depends on 13) The flash memory device of claim 13 wherein the single-bit serial protocol is Inter IC. ### Claim 15 (depends on 13) The flash memory of claim 13 wherein the multiple bit serial protocol specifies concurrent transfer of two bits. ### Claim 16 (depends on 13) The flash memory of claim 13 wherein: a third one of the pins and a fourth one of the pins are inputs/outputs that are addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and the multiple bit serial protocol specifies concurrent transfer of four bits. ### Claim 17 A flash memory comprising: a flash memory array; and an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol; wherein a first one of the pins is configurable with the interface circuit as a data output pin in compliance with the single-bit serial protocol during an output sequence of a “Fast Read” instruction; wherein the first pin and a second one of the pins are configurable with the interface circuit as data output pins in compliance with the multiple-bit serial protocol during an output sequence of a “Fast Read Dual Output” instruction; and wherein the second pin is configurable with the interface circuit as a data input pin in compliance with the single-bit serial protocol during respective input sequences of the “Fast Read” instruction and the “Fast Read Dual Output” instruction. ### Claim 18 A flash memory comprising: a flash memory array; and an interface circuit coupled to the flash memory array, the interface circuit having a clock pin, a chip select pin, and first, second, third and fourth pins, and being selectively compliant with Serial Peripheral Interface protocol and a four-bit serial protocol; wherein the first pin is configurable with the interface circuit as a data output pin and the second pin is configurable with the interface circuit as an input pin for single-bit serial transfer in compliance with the Serial Peripheral Interface protocol; and wherein the first, second, third and fourth pins are further configurable with the interface circuit as input/output pins for four-bit serial transfers that are addressable but unassociated with dedicated address pins in compliance with the four-bit serial protocol. ### Claim 19 (depends on 18) The flash memory of claim 18 wherein: the third pin is further configurable with the interface circuit as a write protect pin in compliance with the Serial Peripheral Interface protocol; and the fourth pin is further configurable with the interface circuit as a hold pin in compliance with the Serial Peripheral Interface protocol. ### Claim 20 A flash memory comprising: a flash memory array; and an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol; wherein a first one of the pins is selectively configurable with the interface circuit as an input in compliance with the single bit serial protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and wherein a second one of the pins is selectively configurable with the interface circuit as a data output in compliance with the single bit serial protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol. ### Claim 21 (depends on 20) The flash memory of claim 20 wherein the single-bit serial protocol is Serial Peripheral Interface. ### Claim 22 (depends on 20) The flash memory of claim 20 wherein the multiple bit serial protocol specifies concurrent transfer of two bits. ### Claim 23 (depends on 20) The flash memory of claim 20 wherein: a third one of the pins and a fourth one of the pins are inputs/outputs that are addressable but unassociated with dedicated address pins in compliance with the multiple bit serial protocol; and the multiple bit serial protocol specifies concurrent transfer of four bits. ### Claim 24 A flash memory comprising: a flash memory array; and an interface circuit coupled to the flash memory array, the interface circuit having a plurality of pins and being selectively compliant with a single-bit serial protocol and a multiple-bit serial protocol; wherein a first one of the pins is configurable with the interface circuit for single-bit serial input in compliance with the single-bit serial protocol; wherein a second one of the pins is configurable with the interface circuit for single-bit serial data output in compliance with the single-bit serial protocol; and wherein the first pin and the second pin are configurable with the interface circuit for multiple-bit serial output that is addressable but unassociated with dedicated address pins in compliance with the multiple-bit serial protocol. ### Claim 25 A packaged flash memory device comprising: an only eight-contact SOIC or MLP package body; a flash memory array contained in the package body; an interface circuit contained in the package body and coupled to the flash memory array, the interface circuit being selectively compliant with a Serial Peripheral Interface protocol and an Enhanced Serial Peripheral Interface protocol; and four or fewer data contacts, a clock contact, and a chip select contact mounted on the package body and coupled to the interface circuit, a first one of the data contacts being selectively configurable with the interface circuit as an input in compliance with the Serial Peripheral Interface protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the Enhanced Serial Peripheral Interface protocol, and a second one of the data contacts being selectively configurable with the interface circuit as a data output in compliance with the Serial Peripheral Interface protocol and as an input/output that is addressable but unassociated with dedicated address pins in compliance with the Enhanced Serial Peripheral Interface protocol. ### Claim 26 A packaged flash memory device operable under either a single-bit serial protocol or a multiple-bit serial protocol, comprising: an only eight-contact SOIC or MLP package body; first and second data contacts, a clock contact, and a chip select contact mounted on the package body; a flash memory array contained in the package body; and an interface circuit contained in the package body and coupled to the flash memory array and to the first and second data contacts, a clock contact, and a chip select contact, the interface circuit being operable under a single-bit serial protocol to establish the first data contact as an input and the second data contact as a data output, and operable under a multiple-bit serial protocol to establish the first and second data contacts as inputs/outputs that are addressable but unassociated with dedicated address pins. ### Claim 27 (depends on 26) The flash memory of claim 26 further comprising a write protect contact and a hold contact mounted on the package body and coupled to the interface circuit. ### Claim 28 (depends on 26) The flash memory of claim 26 further comprising third and fourth data contacts coupled to the interface circuit, the interface circuit being operable under the multiple-bit serial protocol to establish the third and fourth data contacts as inputs/outputs that are addressable but unassociated with dedicated address pins. ### Claim 29 A packaged flash memory device operable under either a single-bit serial protocol or a multiple-bit serial protocol, comprising: an SOIC or MLP package body; a flash memory array contained in the package body; an interface circuit contained in the package body and coupled to the flash memory; a clock contact coupled to the interface circuit; a chip select contact coupled to the interface circuit; and first and second data contacts coupled to the interface circuit, the interface circuit being operable under a single-bit serial protocol to establish the first data contact as an input and the second data contact as a data output, and operable under a multiple-bit serial protocol to establish the first and second data contacts as data outputs that are addressable but unassociated with dedicated address pins.