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US 7,558,145 B2Granted
Word line control for improving read and write margins
AssigneeInfineon Technologies AG
InventorsSetti Shanmukheswara Rao, Biswa Bhusan Sahoo
Life of this patent
Estimating the term…
Abstract
Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the access cycle and to apply the further voltage to a further word line during the first time interval portion of the access cycle and to apply the voltage to the further word line during the further time interval of the access cycle.
Claims18
Apparatus, comprising:
- a supply node to receive a supply voltage of VDD;
- a memory cell coupled to the supply node and including a storage node;
- decoder circuitry coupled to the memory cell to initiate an access cycle to transfer data;
- a first word line coupled to the memory cell to enable a transfer of data between the storage node and a bit line during the access cycle;
- at least one further word line coupled to the memory cell to enable a transfer of data between the storage node and a further bit line during the access cycle;
- and
- a control circuit responsive to the decoder circuitry to divide the access cycle into at least two time interval portions and to apply a first voltage, higher than the supply voltage, to the first word line during a first time interval portion of the access cycle and to apply a second voltage, lower than the first voltage, to the first word line during a second time interval portion of the access cycle and to apply the second voltage to the at least one further word line during the first time interval portion of the access cycle and to apply the first voltage to the at least one further word line during the second time interval portion of the access cycle.
4 more elements
Apparatus, comprising:
- a supply node to receive a supply voltage;
- a memory cell coupled to the supply node and including a storage node;
- decoder circuitry coupled to the memory cell to initiate an access cycle to transfer data;
- a first word line coupled to the memory cell to enable a transfer of data between the storage node and a bit line during the access cycle;
- at least one further word line coupled to the memory cell to enable a transfer of data between the storage node and a further bit line during the access cycle;
- and
- a control circuit responsive to the decoder circuitry to divide the access cycle into at least two time interval portions and to apply a first voltage, higher than the supply voltage, to the first word line during a first time interval portion of the access cycle and to apply a second voltage, lower than the first voltage, to the first word line during a second time interval portion of the access cycle and to apply the second voltage to the at least one further word line during the first time interval portion of the access cycle and to apply the first voltage to the at least one further word line during the second time interval portion of the access cycle,
- wherein the control circuit includes bit line dummy arrays discharged at a faster slew rate than the normal dummy bit lines to divide the access cycle into at least two substantially equal time interval portions.
5 more elements
A method, comprising:
- providing separate word line signals to word line inputs of each port of an n port static memory during an access cycle which is divided into a time interval portion for each port, the memory powered by a supply voltage of VDD;
- sequentially modifying each word line signal during its time interval portion by boosting its word line voltage to a voltage larger than the supply voltage during that port's time interval portion of the access cycle while the other word line signals remain at a lower voltage.
A system, comprising:
- an input device;
- a display device;
- a processor coupled to the input device to receive input data;
- a memory device including supply node to receive a supply voltage of VDD and a memory cell coupled to the supply node and including a storage node;
- decoder circuitry coupled to the memory cell to initiate an access cycle to transfer data;
- a first word line coupled to the memory cell to enable a transfer of data between the storage node and a bit line during the access cycle;
- at least one further word line coupled to the memory cell to enable a transfer of data between the storage node and a further bit line during the access cycle;
- and
- a control circuit to write data into the memory and read data from the memory, the control circuit responsive to the decoder circuitry to divide the access cycle into at least two time interval portions and to apply a first voltage, higher than the supply voltage, to the first word line during a first time interval portion of the access cycle and to apply a second voltage, lower than the first voltage, to the first word line during a second time interval portion of the access cycle and to apply the second voltage to the at least one further word line during the first time interval portion of the access cycle and to apply the first voltage to the at least one further word line during the second time interval portion of the access cycle.
6 more elements
Dependencies are inferred from the claim text.