Memory system, semiconductor memory device and method of driving same

A method of driving a semiconductor memory device comprising a semiconductor substrate;

• first select transistors formed on the surface of said semiconductor substrate;
• first dummy transistors formed above said first select transistors;
• a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function;
• second dummy transistors formed above said memory cell transistors;
• and second select transistors formed above said second dummy transistors;
• wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of data write operation.

A memory system comprising:

• a storage portion including a semiconductor substrate;
• first select transistors formed on the surface of said semiconductor substrate;
• first dummy transistors formed above said first select transistors;
• a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function;
• second dummy transistors formed above said memory cell transistors;
• and second select transistors formed above said second dummy transistors;
• word line drivers for applying a voltage to the gate electrodes of said plurality of memory cell transistors;
• drivers connected to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors to provide the same potential to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors at the time of write operation to write data to said memory cell transistors;
• and
• a select gate driver connected to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors to provide the same potential to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.