US 7,555,091 B1Granted

System and method for providing a clock and data recovery circuit with a self test capability

AssigneeNational Semiconductor Corporation

InventorsLaurence D. Lewicki, Amjad T. Obeidat, Nicolas Nodenot

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Abstract

A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pattern that causes the digital control circuitry of the clock and data recovery circuit to advance or retard the phase of the interpolated clock signal. The test control unit compares the advanced or retarded phase of the interpolated clock signal with a reference clock signal to determine a frequency difference between the two clock signals. The test control unit uses the frequency difference to determine the test status of the clock and data recovery circuit.

Claims18

Dependent claims

A test control unit within a clock and data recovery circuit that comprises a plurality of comparators, a data alignment path unit, a plurality of phase detectors, digital control circuitry, and a plurality of phase interpolators, connected in a loop configuration in which the plurality of comparators are connected to the data alignment path unit and the data alignment path unit is connected to the plurality of phase detectors and the plurality of phase detectors are connected to the digital control circuitry and the digital control circuitry is connected to the plurality of phase interpolators and the plurality of phase interpolators are connected to the plurality of comparators, wherein said test control unit comprises:

test control circuitry that receives from the clock and data recovery circuit signals that indicate an operational status of the clock and data recovery circuit and that determines from the received signals whether the operational status of the clock and data recovery circuit passes or fails a test that is performed by the test control circuitry, wherein said test control circuitry comprises:
first electronic circuitry that causes said clock and data recovery circuit to continuously alter a phase of an interpolated clock signal within said clock and data recovery circuit;
second electronic circuitry that receives at least one preselected bit pattern from a user of said test control unit;
and
third electronic circuitry that imposes said at least one preselected bit pattern on an input of said plurality of phase detectors.

2 more elements

A method for testing a clock and data recovery circuit that comprises a plurality of comparators, a data alignment path unit, a plurality of phase detectors, digital control circuitry, and a plurality of phase interpolators, connected in a loop configuration in which the plurality of comparators are connected to the data alignment path unit and the data alignment path unit is connected to the plurality of phase detectors and the plurality of phase detectors are connected to the digital control circuitry and the digital control circuitry is connected to the plurality of phase interpolators and the plurality of phase interpolators are connected to the plurality of comparators, said method comprising the steps of:

coupling a test control unit to said clock and data recovery circuit;
and
receiving in said test control unit signals from the clock and data recovery circuit that indicate an operational status of the clock and data recovery circuit;
performing in said test control unit a test of the operational status of the clock and data recovery circuit using the received signals;
and
determining whether the operational status of the clock and data recovery circuit passes or fails the test;
wherein performing the test of the operational status of the clock and data recovery circuit comprises:
sending the received signals to said test control unit to cause said clock and data recovery circuit to continuously alter a phase of an interpolated clock signal within said clock and data recovery circuit;
receiving in said test control unit at least one preselected bit pattern from a user of said test control unit;
and
imposing said at least one preselected bit pattern on an input of said plurality of phase detectors.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/973,131Filed 26 Oct 2004
Granted: 30 Jun 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H04L 7/0079
Arrangements for synchronising receiver with transmitter: receiver details
G01R 31/31715
Input or output aspects: testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of…
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…