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US 7,549,033 B2Granted
Dual edge command
AssigneeMicron Technology, Inc.
InventorsJoo S. Choi, Troy A. Manning, Brent Keeth
Life of this patent
Estimating the term…
Abstract
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
Claims42
A method of operating a non-volatile memory device, comprising:
- receiving an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals BA0-BA2, and Row Address signals A0-A11, and wherein the receiving the F-bit word comprises:
- receiving a first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals BA0-BA2, and a first subset of Row Address signals, wherein the receiving the Active command signal includes using a set of Command Pins, and wherein the receiving the Bank Address signals and the first subset of Row Address signals includes using a set of Address Pins;
- and
- receiving a second portion of the F-bit word substantially simultaneous with receiving a second event, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the receiving the second subset of Row Address signals includes using the set of Command Pins and the set of Address Pins;
- performing a memory command, in a non-volatile memory, in response to the received F-bit word;
- sending the first portion of the F-bit word substantially simultaneous with sending the first event by an external controller;
- and
- sending the second portion of the F-bit word substantially simultaneous with sending the second event by the external controller.
5 more elements
A system, comprising:
- at least one non-volatile memory device, comprising:
- means for receiving an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals BA0-BA2, and Row Address signals A0-A11, and wherein the means for receiving the F-bit word comprises:
- means for receiving a first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals BA0-BA2, and a first subset of Row Address signals, wherein the means for receiving the Active command signal includes using a set of Command Pins, and wherein the means for receiving the Bank Address signals and the first subset of Row Address signals includes using a set of Address Pins;
- and
- means for receiving a second portion of the F-bit word substantially simultaneous with receiving a second event, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the means for receiving the second subset of Row Address signals includes using the set of Command Pins and the set of Address Pins;
- means for performing a memory command in response to the received F-bit word;
- means for sending the first portion of the F-bit word substantially simultaneous with sending the first event by an external controller;
- and
- means for sending the second portion of the F-bit word substantially simultaneous with sending the second event by the external controller.
6 more elements
A system, comprising:
- at least one non-volatile memory device, comprising:
- multiple command and address pins;
- wherein the multiple command and address pins are configured to receive a first portion of an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals BA0-BA2, and Row Address signals A0-A11, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals BA0-BA2, and a first subset of Row Address signals, wherein the multiple command and address pins receive the first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the command pins are configured to receive the Active command signal, and wherein the address pins are configured to receive the Bank Address signals BA0-BA2 and the first subset of Row Address signals;
- wherein the multiple command and address pins are configured to receive a second portion of an F-bit word, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the multiple command and address pins receive the second portion of the F-bit word substantially simultaneous with receiving a second event;
- and
- wherein the non-volatile memory device is configured to perform a memory command in response to the received F-bit word;
- at least one external controller;
- wherein the external controller is configured to send the first event, wherein the external controller is configured to send the first portion of the F-bit word substantially simultaneous with sending the first event;
- and
- wherein the external controller is configured to send the second event, wherein the external controller is configured to send the second portion of the F-bit word substantially simultaneous with sending the second event.
7 more elements
A method of operating a non-volatile memory device, comprising:
- receiving an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals, and Row Address signals, wherein the Active command signal comprises CS# low, RAS# low, CAS# high, and WE# high, and wherein the receiving the F-bit word comprises:
- receiving a first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals, and a first subset of Row Address signals, wherein the receiving the Active command signal includes using a set of Command Pins, and wherein the receiving the Bank Address signals and the first subset of Row Address signals includes using a set of Address Pins;
- and
- receiving a second portion of the F-bit word substantially simultaneous with receiving a second event, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the receiving the second subset of Row Address signals includes using the set of Command Pins and the set of Address Pins;
- performing a memory command, in a non-volatile memory, in response to the received F-bit word;
- sending the first portion of the F-bit word substantially simultaneous with sending the first event by an external controller;
- and
- sending the second portion of the F-bit word substantially simultaneous with sending the second event by the external controller.
5 more elements
A system, comprising:
- at least one non-volatile memory device, comprising:
- means for receiving an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists essentially of an Active command signal, Bank Address signals, and Row Address signals, wherein the Active command signal comprises CS# low, RAS# low, CAS# high, and WE# high, and wherein the means for receiving the F-bit word comprises:
- means for receiving a first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals, and a first subset of Row Address signals, wherein the means for receiving the Active command signal includes using a set of Command Pins, and wherein the means for receiving the Bank Address signals and the first subset of Row Address signals includes using a set of Address Pins;
- and
- means for receiving a second portion of the F-bit word substantially simultaneous with receiving a second event, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the means for receiving the second subset of Row Address signals includes using the set of Command Pins and the set of Address Pins;
- means for performing a memory command in response to the received F-bit word;
- means for sending the first portion of the F-bit word substantially simultaneous with sending the first event by an external controller;
- and
- means for sending the second portion of the F-bit word substantially simultaneous with sending the second event by the external controller.
6 more elements
A system, comprising:
- at least one non-volatile memory device, comprising:
- multiple command and address pins;
- wherein the multiple command and address pins are configured to receive a first portion of an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals, and Row Address signals, wherein the Active command signal comprises CS# low, RAS# low, CAS# high, and WE# high, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals, and a first subset of Row Address signals, wherein the multiple command and address pins receive the first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the command pins are configured to receive the Active command signal, and wherein the address pins are configured to receive the Bank Address signals and the first subset of Row Address signals;
- wherein the multiple command and address pins are configured to receive a second portion of an F-bit word, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the multiple command and address pins receive the second portion of the F-bit word substantially simultaneous with receiving a second event;
- and
- wherein the non-volatile memory device is configured to perform a memory command in response to the received F-bit word;
- at least one external controller;
- wherein the external controller is configured to send the first event, wherein the external controller is configured to send the first portion of the F-bit word substantially simultaneous with sending the first event;
- and
- wherein the external controller is configured to send the second event, wherein the external controller is configured to send the second portion of the F-bit word substantially simultaneous with sending the second event.
7 more elements
Dependencies are inferred from the claim text.