Efficient marking of shared cache lines
AssigneeSun Microsystems, Inc.
InventorsRobert E. Cypher, Shailender Chaudhry
Life of this patent
Estimating the term…
Abstract
One embodiment of the present invention provides a system that efficiently marks cache lines in a multi-processor computer system. The system starts by receiving a load request for a cache line from a requesting thread. Upon receiving the load request, the system loads a copy of the cache line into a local cache for the requesting thread. The system then load-marks the copy of the cache line in the local cache by incrementing a reader count value contained in metadata for the copy of the cache line, regardless of the cache coherency protocol status of the copy of the cache line, whereby the system updates the metadata in the local copy of the cache line without obtaining exclusive access to the cache line.
Claims20
An apparatus for efficiently marking cache lines in a multi-processor computer system, comprising:
- a processor;
- a local cache coupled to the processor;
- a memory-control mechanism coupled to the local cache;
- a memory system coupled to the memory-control mechanism;
- wherein the memory-control mechanism is configured to receive a load request for a cache line from a requesting thread;
- upon receiving the request, the memory-control mechanism is configured to load a copy of the cache line from the local cache from the memory system;
- and
- wherein the memory-control mechanism is configured to load-mark the copy of the cache line in the local cache by incrementing a reader count value contained in metadata corresponding to the copy of the cache line regardless of the valid cache coherency protocol status of the copy of the cache line.
A computer system for efficiently marking cache lines in a multi-processor computer system, comprising:
- a processor;
- a local cache coupled to the processor;
- a memory-control mechanism coupled to the local cache;
- a memory system coupled to the memory-control mechanism;
- a mass-storage device coupled to the memory system, wherein the mass storage device is configured to store data and, program code;
- wherein the memory-control mechanism is configured to receive a load request for a cache line from a requesting thread;
- upon receiving the request, the memory-control mechanism is configured to load a copy of the cache line from the local cache from the memory system;
- and
- wherein the memory-control mechanism is configured to load-mark the copy of the cache line in the local cache by incrementing a reader count value contained in metadata corresponding to the copy of the cache line regardless of the valid cache coherency protocol status of the copy of the cache line.
A method for efficiently marking cache lines in a multi-processor computer system, comprising:
- receiving a load request for a cache line from a requesting thread;
- loading a copy of the cache line into a local cache for the requesting thread;
- and
- load-marking the copy of the cache line in the local cache by incrementing a reader count value contained in metadata for the copy of the cache line regardless of the valid cache coherency protocol status of the copy of the cache line;
- whereby the requesting thread can update the metadata in the copy of the cache line without having to obtain exclusive access to the cache line.
Dependencies are inferred from the claim text.