Statistics collection framework for a network processor

An integrated circuit comprising:

• a local memory to store a rule table, the rule table organized with entries comprising a packet offset, a data pattern, and an action;
• a packet data queue to receive packet data;
• a rule fetch unit to fetch rules from the rule table;
• a packet data fetch unit to fetch a segment of packet data from the packet data queue, based on the packet offset fetched by the rule fetch unit;
• match circuitry to compare the packet data segment fetched by the packet data fetch unit with the data pattern fetched by the rule fetch unit;
• an action unit to perform the action fetched by the rule fetch unit when the match circuitry indicates a match between the compared packet data segment and data pattern;
• and
• the local memory also to store a counter table, wherein the action in a rule table entry comprises an index into the counter table, the action unit responding to the counter table index and a match indicated by the match circuitry by incrementing an entry in the counter table referenced by the counter table index.

A method of gathering statistics on packets received by a network processor, the method comprising:

• configuring a core processor to dynamically accept packet rule requests and place corresponding packet rules in a packet rule set area at a first memory region in an addressable memory space, at least one rule in the packet rule set specifying a packet offset, a data pattern, and a counter offset;
• configuring a set of packet processing engines to sequence through the packet rule set, retrieving one of the packet rules from the first memory region and comparing packet data from a received packet, at the offset specified in the retrieved packet rule, to the data pattern specified in the retrieved packet rule, and, when the comparison evaluates true, incrementing a counter, at the counter offset specified in the retrieved packet rule, within a second memory region in the addressable memory space;
• and
• configuring the core processor to retrieve statistics from the counters in the second memory region.

An article of manufacture comprising computer-readable media containing instructions that, when executed by a network processor, cause that network processor to perform a method comprising:

• dynamically accepting packet rule requests at a core processor and placing corresponding packet rules in a packet rule set area at a first memory region in an addressable memory space, at least one rule in the packet rule set specifying a packet offset, a data pattern, and a counter offset;
• sequencing through the packet rule set with a set of packet processing engines, retrieving one of the packet rules from the first memory region and comparing packet data from a received packet, at the offset specified in the retrieved packet rule, to the data pattern specified in the retrieved packet rule, and, when the comparison evaluates true, incrementing a counter, at the counter offset specified in the retrieved packet rule, within a second memory region in the addressable memory space;
• and
• the core processor retrieving statistics from the counters in the second memory region for distribution outside of the network processor.