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AssigneeCanon Kabushiki Kaisha
InventorsYoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
Estimating the term…
To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
A method for logic checking to check an arbitration of an arbiter that is connected to a bus to which at least two master circuits and at least one slave circuit are connected, the method comprising the steps of:
Dependencies are inferred from the claim text.