Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Seung Kim, Chul-Sung Park
Life of this patent
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Abstract
A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.
Claims18
A semiconductor memory device that operates in a first mode and a second mode, the semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arrayed in columns and rows in a matrix;
- a peripheral circuit coupled to the memory cell array and configured to write data to the memory cell array and to read data from the memory cell array;
- and
- a bypass control unit coupled to the peripheral unit, the bypass control unit configured to enable a late write operation and a bypass operation of the peripheral circuit when the semiconductor memory device operates in the first mode and to disable the late write operation and the bypass operation of the peripheral circuit when the semiconductor memory device operates in the second mode.
A data input/output method of a semiconductor memory device operating in a first mode and a second mode, the data input/output method comprising:
- outputting a late write signal and a bypass control signal in response to a second mode write command signal, a first signal, and a clock signal, which are input in the second mode;
- and
- generating the bypass signal in response to the first signal and the bypass control signal,
- wherein the late write signal enables a late write operation when data is input, the bypass signal enables a bypass operation when data is output, and the first signal is generated when a first address, which is input together with a write command in the first mode of the semiconductor memory device, is the same as a second address, which is input following the first address after the semiconductor memory device is converted to the second mode.
Dependencies are inferred from the claim text.