Memory device and method having multiple address, data and command buses

A memory device, comprising:

• an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device;
• a plurality of internal bi-directional data buses that are isolated from each other;
• a data coupling circuit operable to couple write data signals corresponding to write data from the external port to a selected one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from a selected one of the internal data buses to the external port;
• a plurality of banks of memory cells coupled to a respective one of the internal data buses;
• a bank coupling circuit for each of the banks of memory cells, each of the bank coupling circuits being operable to couple the write data signals from the respective internal data bus to the respective bank and to couple the read data signals from the respective bank to the respective one of the internal data buses;
• an addressing circuitry receiving the memory address signals from the external port and being operable to select a memory location in at least one of the banks responsive to the received memory address signals;
• and
• control circuitry coupled to the data coupling circuit and the bank coupling circuit, the control circuitry being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select the internal data bus to which the write data signals are coupled and from which the read data signals are coupled, the control circuitry comprising:
• a flip-flop having a clock input coupled to receive a signal generated responsive to the memory command signals applied to the external port;
• and
• a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal data buses each time the flip-flop toggles.

A method of accessing data in a memory device, comprising:

• coupling a first memory command to the memory device;
• initiating a first memory access in a first bank of memory cells in the memory device responsive to the first memory command, the act of initiating the first memory access comprising prefetching data from the first bank of memory cells to transfer to an external device responsive to the first memory command;
• while the first memory access is being processed, coupling a second memory command to the memory device, the second memory command being different from the first memory command;
• and
• initiating a second memory access in a second bank of memory cells in the memory device responsive to the second memory command while the first memory access is being processed, the second bank being different from the first bank, the act of initiating the second memory access comprising initiating a prefetch of data from the second bank of memory cells responsive to the second memory command while data are being transferred to the external device responsive to the prefetching of data from the first bank of memory cells.

A memory device, comprising:

• an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device;
• a plurality of internal address buses that are isolated from each other;
• an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to either one of the internal address buses;
• a plurality of internal bidirectional data buses that are isolated from each other;
• a data coupling circuit operable to couple write data signals corresponding to write data from the external port to either one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from either one of the internal data buses to the external port;
• a plurality of banks of memory cells coupled to a respective one of the internal address buses;
• a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from either of the internal address buses to the respective bank;
• each of the bank coupling circuits being operable to couple the write data signals from either of the internal data buses to the respective bank and to couple the read data signals from the respective bank to either of the internal data buses;
• and
• a control circuit coupled to the address coupling circuit, the data coupling circuit and the bank coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select either of the internal address buses to which the address signals are coupled, the control circuit further being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select either of the internal data buses to which the write data signals are coupled and from which the read data signals are coupled, the control circuit comprising:
• a flip-flop having a clock input coupled to receive a signal generated responsive to each of the memory command signals being applied to the external port;
• and
• a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal address buses each time the flip-flop toggles.

A memory device, comprising:

• an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device;
• a plurality of internal address buses that are isolated from each other;
• an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to either one of the internal address buses;
• a plurality of internal bidirectional data buses that are isolated from each other;
• a data coupling circuit operable to couple write data signals corresponding to write data from the external port to either one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from either one of the internal data buses to the external port;
• a plurality of banks of memory cells coupled to a respective one of the internal address buses;
• a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from either of the internal address buses to the respective bank;
• each of the bank coupling circuits being operable to couple the write data signals from either of the internal data buses to the respective bank and to couple the read data signals from the respective bank to either of the internal data buses;
• and
• a control circuit coupled to the address coupling circuit, the data coupling circuit and the bank coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select either of the internal address buses to which the address signals are coupled, the control circuit further being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select either of the internal data buses to which the write data signals are coupled and from which the read data signals are coupled, the control circuit comprising:
• a flip-flop having a clock input coupled to receive a signal generated responsive to the memory command signals applied to the external port;
• and
• a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal data buses each time the flip-flop toggles.