US 7,548,472 B2 · Logic embedded memory having registers commonly used by macros

Abstract

A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

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Claims23

Dependent claims

A semiconductor integrated circuit device comprising:

a plurality of memory macros having memory cells which store data,
a nonvolatile storage circuit which stores a plurality of data items including a set value for an internal timer which determines timings of operations of the plurality of memory macros and voltages of internal power supplies in the plurality of memory macros,
a macro-common register block provided outside the plurality of memory macros and having macro-common registers which sequentially distribute memory macro operation specifying signals, which are related to the set value for the internal timer and voltages of the internal power supplies, to the plurality of memory macros, the macro-common registers being connected in serial to the nonvolatile storage circuit to serially store, upon power on, the data items including the set value for the internal timer and voltages of the internal power supplies and stored in the nonvolatile storage circuit, and
memory macro operation setting circuits which are respectively provided in the plurality of memory macros and configured to set operating states of the memory macros according to the memory macro operation specifying signals which are data related to the set value for the internal timer and voltages of the internal power supplies and which are supplied from the macro-common registers, the memory macro operation setting circuits tuning the set value for the internal timer and the voltages of the internal power supplies in the plurality of memory macros.

1 more element

A semiconductor integrated circuit device comprising:

a plurality of memory macros having memory cells which store data,
a plurality of logic circuits which are respectively provided in the plurality of memory macros and each configured to transfer data with respect to a corresponding one of the memory macros, each of the plurality of logic circuits logically processing data read out of a corresponding one of the memory macros and writing the logically processed data to the one of the memory macros,
a nonvolatile storage circuit configured to store a plurality of data items including address data representing a specific one of the plurality of memory macros,
a macro-common register block provided outside the plurality of memory macros and having macro-common registers which sequentially distribute address signals and a monitor signal, which are based on the address data, to the plurality of memory macros, the macro-common registers being connected in series to the nonvolatile storage circuit to serially store, upon power on, the address data stored in the nonvolatile storage circuit, and
memory macro operation setting circuits which are respectively provided in the plurality of memory macros and configured to set operating states of the memory macros according to the address signals and the monitor signal, the memory macro operation setting circuits having adders or subtracters each supplied with the address signals and in which an output signal of the adders or subtracters is supplied to a next-stage memory macro,
an AND circuit which derives a logical product of inverted signals of the address signals input to the adder or subtracter and the monitor signal, and
a transfer gate connected at one end to an internal power supply, connected at the other end to a monitoring pad, and controlled by an output signal of the AND circuit.

4 more elements

Dependencies are inferred from the claim text.

Description5,664 words

Summary707 words

#This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-008138, filed Jan. 14, 2005, the entire contents of which are incorporated herein by reference.

#1. Field of the Invention

#This invention relates to a semiconductor integrated circuit device such as a logic embedded memory having a logic circuit and a memory integrated in one chip.

Brief description of the drawings8 figures

#FIG. 2 is a circuit diagram showing an extracted data program circuit which programs data into macro-common registers shown in FIG. 1;

#FIG. 3 is a block diagram showing a concrete example of a portion of signal lines which transmit macro operation state specifying signals in a memory macro shown in FIG. 1;

Detailed description4,707 words

#FIG. 1 is a block diagram showing the schematic configuration of an extracted main portion of a logic embedded memory, for illustrating a semiconductor integrated circuit device according to a first embodiment of this invention. The logic embedded memory includes a macro-common register block 11, memory macros 12-1 to 12-n, logic circuits 13-1 to 13-n and storage circuit (nonvolatile memory) 14.

#The macro-common register block 11 is commonly used by the memory macros 12-1 to 12-n. The macro-common register block 11 includes macro-common registers 15a to 15d which latch data FIN such as setting values of internal timers and voltages of internal power supplies stored in the storage circuit 14 at the turn-ON time of the power supply. The macro-common registers 15a to 15d form a serial chain. That is, the macro-common registers 15a to 15d are configured so that data FIN input from the storage circuit 14 to the macro-common register 15a will be sequentially transferred from the preceding-stage macro-common register to the next-stage macro-common register. In this example, for simplicity of the explanation, n memory macros and four macro-common registers are provided, but a desired number of memory macros and macro-common registers can be used if they are provided in a plural form.

#The memory macros 12-1 to 12-n are serially connected to sequentially distribute memory macro operation specifying signals CSa to CSd output from the macro-common registers 15a to 15d to the memory macros 12-1 to 12-n in a chain form.

Facts

Application

11/190,008Filed 27 Jul 2005

Priority

JP 2005-00813814 Jan 2005

Published

US 2006/0161744 A120 Jul 2006

Granted

16 Jun 2009

Term ended

2 Apr 2026

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 249 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification6 codes

G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/1012
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data reordering during…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 2207/104
Aspects relating to interfaces of memory device to external buses: embedded memory devices, e.g. memories with a processing device on the same die…

Timeline

14 Jan 2005Priority claimedJP 2005-008138
27 Jul 2005Application filedUS 11/190,008
31 Aug 2005Assigned to Kabushiki Kaisha Toshibaassignment of assignor's interest
20 Jul 2006PublishedUS 2006/0161744 A1
16 Jun 2009GrantedUS 7,548,472 B2
2 Apr 2026Term endedEstimated, includes 249 days of adjustment

Logic embedded memory having registers commonly used by macros

Life of this patent

Logic embedded memory having registers commonly used by macros

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims23

Description5,664 words

Drawings

Classification6 codes

Life of this patent

Description5,664 words