Method and apparatus for adjusting the timing of an electronic circuit

An apparatus for adjusting the data output timing of an electronic device, comprising:

• a memory array;
• and
• data output circuitry, wherein the data output circuitry is configured to perform the steps comprising:
• receiving a trigger signal;
• based on the trigger signal, determining whether the electronic device is operating in one of a first mode and a second mode, the first and second modes being differentiated by a rate at which the trigger signal propagates relative to a predetermined standard;
• if the electronic device is operating in the first mode, triggering an output of data with a first clock signal;
• and
• if the memory device is operating in the second mode triggering the output of the data with a second clock signal, wherein the second clock signal is delayed relative to the first clock signal.

A memory device, comprising:

• a clock signal input configured to receive a clock signal, and coupled to a first data input of a selection circuit and to an input of a delay device;
• an output of the delay device coupled to a second data input of the selection circuit;
• a compensated reference delay circuit configured to receive a trigger signal, and having at least one delay component being powered by a regulated voltage;
• an uncompensated delay circuit configured to receive the trigger signal, and having at least one delay component being powered by an unregulated voltage;
• an output of the compensated reference delay circuit being coupled to a first input of a phase detector circuit,
• an output of the uncompensated delay circuit being coupled to a second input of a phase detector circuit, wherein the phase detector circuit is configured to compare the phase of signals received from the compensated reference delay circuit and the uncompensated delay circuit, and in response to the comparison send a select signal to the selection circuit;
• and
• an output of the selection circuit coupled to an input of a data output latch, wherein in response to the select signal the selection circuit is configured to couple at least one of the first input of the selection circuit to the input of the data latch and the second input of the selection circuit to the input of the data latch.

A method for adjusting the data output timing of a memory device, comprising:

• generating a plurality of delayed clock signals using a clock signal;
• routing a trigger signal through a compensated delay chain to generate a compensated delayed trigger signal;
• routing the trigger signal through an uncompensated delay chain to generate a plurality of uncompensated delayed trigger signals;
• comparing a phase of the compensated delayed trigger signal with phases of the plurality of uncompensated delayed trigger signals;
• and
• based on the comparison of the phases, selecting at least one of the clock signal or the plurality of delayed clock signals to trigger a data output latch.

An apparatus for adjusting the data output timing of a memory device, comprising:

• a memory array;
• and
• data output circuitry configured to perform steps comprising:
• receiving a clock signal and a trigger signal;
• generating a plurality of delayed clock signals using the clock signal;
• routing the trigger signal through a compensated delay chain to generate a compensated delayed trigger signal;
• routing the trigger signal through an uncompensated delay chain to generate a plurality of uncompensated delayed trigger signals;
• comparing a phase of the compensated delayed trigger signal with phases of the plurality of uncompensated delayed trigger signals;
• and
• based on the comparison of the phases, selecting at least one of the clock signal or the plurality of delayed clock signals to trigger a data output latch coupled to the memory array.