Semiconductor memory and operation method for same

A semiconductor memory comprising:

• a memory core including dynamic memory cells, a bit line connected with said dynamic memory cells, and a precharge circuit having an nMOS transistor connecting said bit line with a precharge voltage line;
• a switch circuit which outputs one of a first voltage and a second voltage higher than the first voltage in response to a switch control signal;
• and
• a signal generating circuit which generates a bit line resetting signal to be supplied to the gate of said nMOS transistor and which sets a high-level voltage of said bit line resetting signal to one of said first and second voltages outputted from said switch circuit,
• wherein said first voltage is set during a first precharge operation corresponding to a first request and said second voltage is set during a second precharge operation corresponding to a second request.