Methods of biasing a multi-level-cell memory
AssigneeMacronix International Co., Ltd.
InventorChao-I Wu
Life of this patent
Estimating the term…
Abstract
Methods are described for double-side-bias of multi-level-cell memory devices comprising a NAND array that comprises a plurality of charge trapping memory cells. A memory device is programmed by a double-side-bias electron injection technique and is erased by a double-side-bias hole injection technique. Each charge trapping memory cell includes 2n logic states, such as four binary logic states of a logic 00 state, a logic 01 state, a logic 10 state and a logic 11 state. The memory device can be programmed by a double-side-bias multi-level-cell program method either with a variable DSB (Vd/Vs) voltage or with a variable gate bias voltage Vg.
Claims18
A method of biasing a multi-level-cell (MLC) memory device having a plurality of charge trapping memory cells in a memory array, each charge trapping memory cell in the plurality of charge trapping memory cells having 2n logic states including a first logic state, a second logic state, a third logic state, a fourth logic state, each charge trapping memory cell having a first charge trapping site for storing a first bit and a second charge trapping site for storing a second bit, comprising:
- programming the plurality of charge trapping memory cells by simultaneously biasing a respective source terminal and a respective drain terminal in each of the plurality of charge trapping memory cells and applying a gate voltage to a respective terminal in each of the plurality of charge trapping memory cells;
- determining a bit in each of the plurality of charge trapping memory cells that has been over-programmed by reading a voltage value of the bit and comparing with a reference voltage value, the over-programmed bit having a source terminal, a drain terminal and a gate terminal;
- erasing the over-programmed bit by biasing simultaneously the source terminal and the drain terminal of the over-programmed bit;
- and
- reprogramming the over-programmed bit that is erased during the erasing operation.
A method of biasing a multi-level-cell (MLC) memory device having a plurality of charge trapping memory cells in a memory array, each charge trapping memory cell having a first charge trapping site for storing a first bit and a second charge trapping site for storing a second bit, the combination of the first and second bits providing a first multi-level-cell state, a second multi-level-cell state, a third multi-level-cell state, a fourth multi-level-cell state, comprising:
- programming the plurality of charge trapping memory cells by simultaneously biasing a respective source terminal and a respective drain terminal in each charge trapping memory cell and applying a gate voltage to a respective terminal in each charge trapping memory cell;
- determining a bit in each charge trapping memory cell of the plurality of charge trapping memory cells that has been over-programmed by reading a voltage value of the bit and comparing with a reference voltage value, the over-programmed bit having a source terminal, a drain terminal and a gate terminal;
- erasing the over-programmed bit by biasing simultaneously the source terminal and the drain terminal of the over-programmed bit in the selected charge trapping memory cell;
- and
- reprogramming the over-programmed bit that is erased during the erasing operation.
Dependencies are inferred from the claim text.