Combo memory cell

A combo memory cell having a random access mode and a read only mode and first and second logic states wherein voltage level of the first logic state exceeds the second logic state, comprising:

• a static random access memory cell, comprising:
• a first inverter comprising a first PMOS transistor and a first NMOS transistor, with gates thereof commonly connected to a first input node and drains thereof commonly connected to a first output node;
• and
• a second inverter comprising a second PMOS transistor and a second NMOS transistor, with gates thereof commonly connected to a second input node and drains thereof commonly connected to a second output node;
• wherein the first input node and the second output node are connected, as are the second input node and the first output node;
• and
• first and second mask-ROM code programmers respectively coupled to the sources of the first PMOS and NMOS transistors.

A combo memory cell having a random access mode and a read only mode and first and second logic states wherein voltage level of the first logic state exceeds the second logic state, comprising:

• a static random access memory cell, comprising:
• a first MOS transistor having a source coupled to a write bit line and a gate coupled to a write word line;
• a second MOS transistor having a gate coupled to a drain of the first MOS transistor;
• and
• a third MOS transistor having a source coupled to a drain of the second MOS transistor, a gate coupled to a read word line, and a drain coupled to a read bit line;
• and
• a mask-ROM code programmer coupled to the source of the second MOS transistor.