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US 7,548,455 B2Granted
Multi-valued logic/memory cells and methods thereof
AssigneeRochester Institute of Technology
InventorsReinaldo Vega, Stephen Sudirgo
Life of this patent
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Abstract
A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to the tunnel diodes and the driving system is coupled to the tunnel diodes and the loading system. The driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states.
Claims20
A memory cell comprising:
- two or more tunnel diodes coupled together;
- a loading system coupled to the tunnel diodes;
- and
- a driving system coupled to the tunnel diodes and the loading system, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states and wherein at least a portion of the driving system comprises at least part of the loading system in at least one quadrant and at least another portion of the driving system comprises at least part of the loading system in at least one other quadrant.
1 more element
A memory cell comprising:
- two or more tunnel diodes coupled together;
- a loading system coupled to the tunnel diodes;
- and
- a driving system coupled to the tunnel diodes and the loading system, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein an anode of one of the two or more tunnel diodes is coupled to an anode of another one of the two or more tunnel diodes;
- wherein the loading system comprises one or more resistors coupled in series with the two or more tunnel diodes;
- and
- wherein the driving system comprises at least one voltage source that provides four or more voltages that drive the sense node between at least four or more of the substantially stable logic states based on the four or more voltages.
5 more elements
A memory cell comprising:
- two or more tunnel diodes coupled together;
- a loading system coupled to the tunnel diodes;
- and
- a driving system coupled to the tunnel diodes and the loading system, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein a cathode of one of the two or more tunnel diodes is coupled to a cathode of another one of the two or more tunnel diodes;
- and
- wherein the loading system and the driving system comprise at least one p type field effect transistor and at least one n type field effect transistor, a source of each of the p type field effect transistor and the n type field effect transistor are coupled to the two or more tunnel diodes, the p type field effect transistor and the n type field effect transistor drive the sense node between at least four or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the p type field effect transistor and the n type field effect transistor.
4 more elements
A memory cell comprising:
- two or more tunnel diodes coupled together;
- a loading system coupled to the tunnel diodes;
- and
- a driving system coupled to the tunnel diodes and the loading system, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the loading system comprises one or more resistors coupled in series with the two or more tunnel diodes;
- and
- wherein the driving system comprises two or more field effect transistors that drive the sense node between the three or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the two or more field effect transistors.
4 more elements
A memory cell comprising:
- two or more tunnel diodes coupled together;
- a loading system coupled to the tunnel diodes;
- and
- a driving system coupled to the tunnel diodes and the loading system, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the loading system comprises at least one load field effect transistor;
- wherein the driving system comprises at least one drive field effect transistor coupled in parallel with at least one of the two or more tunnel diodes, the drive field effect transistor drives the sense node between the three or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the drive field effect transistor.
3 more elements
A method for making a memory cell, the method comprising:
- coupling two or more tunnel diodes together;
- coupling a loading system to the tunnel diodes;
- and
- coupling a driving system to the loading system and the tunnel diodes, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states, and wherein at least a portion of the driving system comprises at least part of the loading system in at least one quadrant and at least another portion of the driving system comprises at least part of the loading system in at least one other quadrant.
1 more element
A method for making a memory cell, the method comprising:
- coupling two or more tunnel diodes together;
- coupling a loading system to the tunnel diodes;
- and
- coupling a driving system to the loading system and the tunnel diodes, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the coupling two or more tunnel diodes together further comprises coupling an anode of one of the two or more tunnel diodes to an anode of another one of the two or more tunnel diodes;
- wherein the loading system comprises one or more resistors and the coupling the loading system to the tunnel diodes further comprises coupling the one or more resistors in series with the two or more tunnel diodes;
- and
- wherein the driving system comprises at least one voltage source and the coupling a driving system to the loading system and the tunnel diodes comprises coupling the voltage source to the one or more resistors and the tunnel diodes, the at least one voltage source provides four or more voltages that drive the sense node between at least four or more of the substantially stable logic states based on the four or more voltages.
5 more elements
A method for making a memory cell, the method comprising:
- coupling two or more tunnel diodes together;
- coupling a loading system to the tunnel diodes;
- and
- coupling a driving system to the loading system and the tunnel diodes, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the coupling two or more tunnel diodes together further comprises coupling a cathode of one of the two or more tunnel diodes to a cathode of another one of the two or more tunnel diodes;
- wherein the loading system and the driving system comprise at least one p type field effect transistor and at least one n type field effect transistor;
- and
- wherein the coupling the loading system to the tunnel diodes and the coupling the driving system to the loading system and the tunnel diodes further comprise coupling a source of each of the p type field effect transistor and the n type field effect transistor to the two or more tunnel diodes, the p type field effect transistor and the n type field effect transistor drive the sense node between at least four or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the p type field effect transistor and the n type field effect transistor.
5 more elements
A method for making a memory cell, the method comprising:
- coupling two or more tunnel diodes together;
- coupling a loading system to the tunnel diodes;
- and
- coupling a driving system to the loading system and the tunnel diodes, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the loading system comprises one or more resistors and the coupling the loading system to the tunnel diodes further comprises coupling the one or more resistors in series with the two or more tunnel diodes;
- and
- wherein the driving system comprises two or more field effect transistors that drive the sense node between the three or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the two or more field effect transistors.
4 more elements
A method for making a memory cell, the method comprising:
- coupling two or more tunnel diodes together;
- coupling a loading system to the tunnel diodes;
- and
- coupling a driving system to the loading system and the tunnel diodes, wherein at least the driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states;
- wherein the loading system comprises at least one load field effect transistor;
- and
- wherein the driving system comprises at least one drive field effect transistor and the coupling a driving system to the loading system and the tunnel diodes further comprises coupling at least one drive field effect transistor in parallel with at least one of the two or more tunnel diodes, the drive field effect transistor drives the sense node between the three or more of the substantially stable logic states at least based on one or more inputs to a gate and a drain of the drive field effect transistor.
4 more elements
Dependencies are inferred from the claim text.