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US 7,548,453 B2Granted
Memory array with readout isolation
AssigneeContour Semiconductor, Inc.
InventorEric Nestler
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.
Claims16
An information-storage circuit comprising:
- a first set of generally parallel conductive lines;
- a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;
- a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;
- and
- interface circuitry for providing an electrically-isolated interface to the information-storage circuit.
2 more elements
A method for accessing an information-storage circuit without interference from external loading effects, the method comprising:
- providing a first set of generally parallel conductive lines;
- providing a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;
- providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;
- and
- providing interface circuitry for providing an electrically-isolated interface to the information-storage circuit.
2 more elements
Dependencies are inferred from the claim text.