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US 7,548,446 B2Granted
Phase change memory device and associated wordline driving circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHye-jin Kim, Du-eung Kim, Beak-hyung Cho, Hyung-rok Oh
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Abstract
A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.
Claims30
A semiconductor memory device, comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals;
- wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level, wherein second transistor includes a first terminal and a second terminal, and wherein the second terminal is connected to receive an inverted address signal.
2 more elements
A semiconductor memory device, comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals;
- wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level
- wherein the first transistor has a first terminal connected to a power supply providing the first voltage level, a gate connected to a corresponding global wordline, and a second terminal connected to the corresponding sub-wordline;
- wherein the semiconductor memory device further comprises m first inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to respective second terminals of the second transistors in the wordline driving circuits, and m second inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to the respective second terminals of the second transistors in the wordline driving circuits;
- wherein the m first inverters have output terminals connected to respective output terminals of the m second inverters.
5 more elements
A semiconductor memory device, comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals;
- wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level;
- wherein the first transistor has a first terminal connected to a power supply providing the first voltage level, a gate connected to ground, and a second terminal connected to a corresponding sub-wordline;
- and,
- wherein the second transistor has a first terminal connected to the second terminal of the first transistor, a gate connected to a corresponding global wordline, and a second terminal.
5 more elements
A semiconductor memory device comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- a wordline driving unit driving the sub-wordlines;
- wherein the wordline driving unit comprises n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals, wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level, wherein second transistor includes a first terminal and a second terminal, and wherein the second terminal is connected to receive an inverted address signal.
2 more elements
A semiconductor memory device comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- a wordline driving unit driving the sub-wordlines;
- wherein the wordline driving unit comprises n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals;
- wherein each of the wordline driving circuits comprises a first transistor having a first terminal connected to a power supply providing the first voltage level, a gate connected to a corresponding global wordline, and a second terminal connected to the corresponding sub-wordline, and a second transistor having a first terminal connected to the second terminal of the first transistor, a gate connected to the corresponding global wordline, and a second terminal;
- and
- wherein said semiconductor memory device further comprises m first inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to respective second terminals of the second transistors in the wordline driving circuits, and m second inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to the respective second terminals of the second transistors in the wordline driving circuits.
5 more elements
A semiconductor memory device comprising:
- n global wordlines, where n is a positive integer;
- n groups of m sub-wordlines, where m is a positive integer;
- and,
- a wordline driving unit driving the sub-wordlines;
- wherein the wordline driving unit comprises n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels of the global wordlines and m address signals;
- and
- wherein each of the wordline driving circuits comprises:
- a first transistor having a first terminal connected to a power supply providing the first voltage level, a gate connected to ground, and a second terminal connected to a corresponding sub-wordline;
- and,
- a second transistor having a first terminal connected to the second terminal of the first transistor, a gate connected to a corresponding global wordline, and a second terminal.
7 more elements
A semiconductor memory device, comprising:
- a plurality of memory cell blocks, each receiving n global wordlines and n groups of m sub-wordlines corresponding to the n global wordlines;
- a plurality of wordline driving units corresponding to the plurality of memory cell blocks and adapted to control voltage levels of the sub-wordlines received by each memory cell block;
- and,
- a first decoding unit receiving m address signals and applying the m address signals to the wordline driving units;
- wherein each of the wordline driving units comprises n groups of m wordline driving circuits, wherein each of the wordline driving circuits is adapted to control the voltage level of a corresponding sub-wordline in response to a logic state of a corresponding one of the global wordlines and a corresponding one of the m address signals, wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level, wherein second transistor includes a first terminal and a second terminal, and wherein the second terminal is connected to receive an inverted address signal.
2 more elements
A semiconductor memory device, comprising:
- a plurality of memory cell blocks, each receiving n global wordlines and n groups of m sub-wordlines corresponding to the n global wordlines;
- a plurality of wordline driving units corresponding to the plurality of memory cell blocks and adapted to control voltage levels of the sub-wordlines received by each memory cell block;
- and,
- a first and a second decoding unit receiving m address signals and applying the m address signals to the wordline driving units;
- wherein each of the wordline driving units comprises n groups of m wordline driving circuits, wherein each of the wordline driving circuits is adapted to control the voltage level of a corresponding sub-wordline in response to a logic state of a corresponding one of the global wordlines and a corresponding one of the m address signals;
- wherein each of the wordline driving circuits comprises a first transistor having a first terminal connected to a power supply providing the first voltage level, a gate connected to a corresponding global wordline, and a second terminal connected to the corresponding sub-wordline, and a second transistor having a first terminal connected to the second terminal of the first transistor, a gate connected to the corresponding global wordline, and a second terminal
- wherein the first decoding unit comprises m first inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to respective second terminals of the second transistors in the wordline driving circuits;
- and
- wherein the second decoding unit comprises m second inverters respectively receiving and inverting the m address signals and outputting the inverted m address signals to the respective second terminals of the second transistors in the wordline driving circuits.
6 more elements
A semiconductor memory device, comprising:
- a plurality of memory cell blocks, each receiving n global wordlines and n groups of m sub-wordlines corresponding to the n global wordlines;
- a plurality of wordline driving units corresponding to the plurality of memory cell blocks and adapted to control voltage levels of the sub-wordlines received by each memory cell block;
- and,
- a first decoding unit receiving m address signals and applying the m address signals to the wordline driving units;
- wherein each of the wordline driving units comprises n groups of m wordline driving circuits, wherein each of the wordline driving circuits is adapted to control the voltage level of a corresponding sub-wordline in response to a logic state of a corresponding one of the global wordlines and a corresponding one of the m address signals;
- wherein each of the wordline driving circuits comprises:
- a first transistor having a first terminal connected to a power supply supplying the first voltage level, a gate connected to ground voltage, and a second terminal connected to a corresponding sub-wordline;
- and,
- a second transistor having a first terminal connected to the second terminal of the first transistor, a gate connected to a corresponding global wordline, and a second terminal.
6 more elements
Dependencies are inferred from the claim text.