Thin film transistor array panel and display device having particular data lines and pixel arrangement

A liquid crystal panel assembly comprising:

• a plurality of pixels arranged in the form of a matrix and each having a pixel electrode and a switching element connected to the pixel electrode;
• a plurality of pairs of gate lines connected to the switching elements and extending in the row direction, each pair of the gate lines being connected to switching elements in a pixel row;
• and
• a plurality of data lines connected to the switching elements and extending in the column direction, the data line being connected to the switching elements of the pixels in at least two adjacent pixel columns;
• wherein the respective data lines are diagonally elongated, and the polarities of the data voltages flowing through adjacent data lines are opposite to each other;
• and wherein with the apparent inversion of the pixels, polarity types of the pixels are altered per a plurality of the pixel columns.

A display device comprising:

• a plurality of pixels arranged in the form of a matrix and each having a pixel electrode and a switching element connected to the pixel electrode;
• a plurality of pairs of gate lines connected to the switching elements and extending in the row direction, each pair of the gate lines being connected to switching elements in a pixel row;
• and
• a plurality of data lines connected to the switching elements via terminal lines and extending in the column direction, the data line being connected to the switching elements of the pixels in at least two adjacent pixel columns;
• wherein the respective data lines are horizontally bent between the two adjacent gate lines, and the polarities of the data voltages flowing through the adjacent data lines are opposite to each other;
• and wherein with the apparent inversion of the pixels, polarity types of the pixels are altered per a plurality of the pixel columns.

A display device comprising:

• a plurality of pixels arranged in the form of a matrix and each having a pixel electrode and a switching element connected to the pixel electrode;
• a plurality of pairs of gate lines connected to the switching elements and extending in the row direction, each pair of the gate lines being connected to switching elements in a pixel row;
• and
• a plurality of data lines connected to the switching elements via terminal lines and extending in the column direction, the data line being connected to the switching elements of the pixels in at least two adjacent pixel columns;
• wherein the respective data lines are diagonally elongated and the polarities of the data voltages flowing through the adjacent data lines are opposite to each other;
• wherein with the apparent inversion of the pixels, polarity types are altered per a plurality of the pixel columns.

A liquid crystal panel assembly comprising:

• a plurality of pixels arranged in the form of a matrix and each having a pixel electrode and a switching element connected to the pixel electrode;
• a plurality of pairs of gate lines connected to the switching elements and extending in the row direction, each pair of the gate lines being connected to switching elements in a pixel row;
• and
• a plurality of data lines connected to the switching elements and extending in the column direction, the data line being connected to the switching elements of the pixels in at least two adjacent pixel columns;
• wherein the respective data lines are horizontally bent between the two adjacent gate lines associated with two adjacent pixel rows, and
• wherein the respective data lines are bent and elongated between two adjacent gate lines in a first horizontal direction, and vertically extend between the two adjacent pixel columns, followed by being bent and elongated between two adjacent gate lines in a second horizontal direction, and
• wherein the two pixels adjacent to each other in the row direction are connected to the same data line, and
• wherein the switching elements of the two pixels adjacent to each other in the row direction are located opposite to each other with respect to the pixel electrode, and
• wherein the two pixels arranged between the two adjacent data lines in the row direction (“the pixels as a unit pixel pair”) are connected to different data lines, and wherein the pixels of the unit pixel pair are connected to the same gate line.