Demodulator circuit for digital television and demodulation method

A demodulation circuit for a digital television receiving system, comprising:

• a polyphase filter for converting a data rate of a digital intermediate frequency signal into a desired data rate of the digital intermediate frequency signal in response to an address selection signal, and for dividing and outputting the digital intermediate frequency signal into a first signal having a real number component and a second signal having an imaginary number component;
• a complex multiplication unit for multiplying the first and second signals by a complex sinewave obtained from a restored carrier so as to remove frequency offsets from the first and second signals, and for generating a first baseband signal and a second baseband signal as a result of removing the frequency offsets;
• a carrier restoration circuit for detecting the frequency offsets of the carrier from the first and second baseband signals and for generating the complex sinewave that is proportional to the frequency offsets;
• a matched filter for filtering the first and second baseband signals to control signal-to-noise ratios thereof;
• a sort circuit for shifting frequencies of outputs from the matched filter;
• a direct current (DC) removal circuit that combines outputs of the sort circuit and removes a direct current component from a result of the combination;
• a sampling rate control circuit for changing a sampling rate of an output of the DC removal circuit and for outputting the result;
• and
• a symbol timing restoration (STR) circuit for measuring a timing error in related symbols of the output of the DC removal circuit and for generating the address selection signal that is proportional to the timing error, in response to a carrier restoration signal that is generated by the carrier restoration circuit and for indicating restoration of the carrier.