Gate driver circuit and display device having the same

A display device comprising:

• a display panel displaying an image in response to a gate signal and a data signal;
• a gate driver circuit outputting the gate signal;
• and
• a data driver circuit outputting the data signal, wherein the gate driver circuit includes:
• a first shift register including a plurality of first stages, the first shift register applying a (4n−3)-th gate signal and a (4n−2)-th gate signal to a (4n−3)-th gate line and a (4n−2)-th gate line, respectively, in response to a first clock signal, a second clock signal, and a third clock signal, the second clock signal having a delayed phase by 1H time with respect to the first clock signal, and the third clock signal having opposite phase to the first clock signal;
• and
• a second shift register including a plurality of second stages, the second shift register applying a (4n−1)-th gate signal and a 4n-th gate signal to a (4n−1)-th gate line and a 4n-th gate line, respectively, in response to the first clock signal, the third clock signal, and a fourth clock signal, the fourth clock signal having opposite phase to the second clock signal, wherein n is a natural number.

A display device comprising:

• a display panel including a plurality of gate lines each having a first end and a second end;
• a first shift register responding to a first clock signal and a second clock signal on the first end of the gate lines, and responding to a third clock signal on the second end of the gate lines;
• and,
• a second shift register responding to the third clock signal and a fourth clock signal on the second end of the gate lines, and responding to the first clock signal on the first end of the gate lines.