Digitally controlled ring oscillator
AssigneeInternational Rectifier Corporation
InventorsSergio Morini, Raffaele Cannizzaro
Life of this patent
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Abstract
A ring oscillator for generating an output signal, comprising a plurality of serially connected main elements for selectively delaying a signal input thereto, each of the plurality of main elements having two circuit paths, a first path including at least one time-delay element for delaying a signal input thereto and a second circuit path bypassing the first circuit path; and a multiplexor (MUX) having a first input coupled to the first circuit path including the at least one time-delay element and a second input coupled to the second circuit path, the MUX selecting the first or second inputs of a plurality of inputs and outputting an output signal.
Claims18
A ring oscillator for generating an output signal, comprising:
- a plurality of serially connected main elements for selectively delaying a signal input thereto, each of the plurality of main elements having:
- two circuit paths, a first path including at least one time-delay element for delaying the signal input thereto to produce a delayed signal input;
- a second circuit path bypassing the first circuit path;
- a multiplexor (MUX) having a first input coupled to the first circuit path including the at least one time-delay element and a second input coupled to the second circuit path, the MUX selecting the first or second inputs and outputting an output signal;
- and
- a selector circuit for selecting the first or second input of the multiplexor, said selector circuit latching and outputting a received data signal upon receiving a clock signal, and
- wherein the clock signal is generated by a logic circuit receiving said signal input and said delayed signal input, whereby the clock signal is only generated to latch said received data signal when both said signal input and said delayed signal input will not cause said multiplexor to select one of said first and second inputs when a pulse is present on one of said first and second inputs.
A method for controlling a ring oscillator for generating an output signal, the ring oscillator comprising a plurality of serially disposed main elements each comprising first and second circuit paths, a multiplexor (MUX) having first and second inputs connected respectively to the first and second circuit paths, and a selector circuit, the method comprising the steps of:
- providing an input signal on the first and second circuit paths of the main element;
- generating a delayed signal on the first path;
- and
- selecting, using the MUX, a desired path of the first and second circuit paths corresponding to a selected mode of the main element, and
- the step of selecting comprising selecting, using the selector circuit, the first or second input of the multiplexor, said selector circuit latching and outputting a received data signal upon receiving a clock signal, and wherein the clock signal is generated by a logic circuit receiving said input signal and said delayed signal, whereby the clock signal is only generated to latch said received data signal when both said input signal and said delayed signal will not cause said multiplexor to select one of said first and second inputs when a pulse is present on one of said first and second inputs.
A ring oscillator for generating an output signal, comprising:
- a plurality of main elements for selectively delaying a signal input thereto, each of the plurality of main elements having:
- a first transmission path having at least one time-delay element for delaying the signal input thereto to produce a delayed signal input;
- a second transmission path having substantially no delay;
- a multiplexor (MUX) having a first input coupled to the first transmission path, a second input coupled to the second transmission path, and a select input for selecting the first or a second transmission path and outputting a corresponding signal;
- and
- a selector circuit for selecting the first or second input of the multiplexor, said selector circuit latching and outputting a received data signal upon receiving a clock signal, and
- wherein the clock signal is generated by a logic circuit receiving said signal input and said delayed signal input, whereby the clock signal is only generated to latch said received data signal when both said signal input and said delayed signal input will not cause said multiplexor to select one of said first and second inputs when a pulse is present on one of said first and second inputs.
Dependencies are inferred from the claim text.