Dividerless PLL architecture
AssigneeSilicon Laboratories Inc.
InventorDouglas R. Frey
Life of this patent
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Abstract
A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.
Claims38
A method comprising:
- generating a phase-locked loop (PLL) output signal that is a frequency multiple, greater than one, of a reference clock signal supplied to the PLL;
- operating the PLL in a first mode in which an output of a feedback divider is compared with the reference clock signal to lock the PLL output signal to the reference clock signal;
- and
- operating the PLL in a second mode after lock is achieved in the first mode to generate the PLL output signal without using the feedback divider while remaining locked to the reference signal.
A phase-locked loop (PLL) comprising a controllable oscillator, the phase-locked loop operable to compare an output signal of the controllable oscillator to a reference clock signal supplied to the phase-locked loop in a phase detector, adjust the controllable oscillator according to the comparison, and supply as the output signal of the controllable oscillator a frequency multiple greater than one of the reference clock signal;
- wherein the PLL is operable, after lock is achieved between the output signal and the reference clock signal, to generate the output signal without using a feedback divider while remaining locked to the reference clock signal.
A phase-locked loop (PLL), operable in a first mode, to lock to a reference clock signal using a feedback divider in the PLL and operable in a second mode with the feedback divider disconnected from the PLL, to generate a PLL output signal that is a frequency multiple, greater than one, of the reference clock signal.
Dependencies are inferred from the claim text.