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US 7,548,113 B2Granted
Apparatus, amplifier, system and method for receiver equalization
AssigneeIntel Corporation
InventorKen Drottar
Life of this patent
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Abstract
In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.
Claims65
A system comprising:
- a transmitter;
- a receiver;
- and
- a transmission line coupled to the transmitter and the receiver;
- the receiver including:
- an amplifier;
- and
- a delay and gain circuit coupled to an output of the amplifier, wherein
- an output of the delay and gain circuit is fed back to the amplifier;
- wherein the amplifier includes a first, a second and a third pMOS transistor and a first, a second and a third nMOS transistor;
- wherein a gate of the first pMOS transistor and a gate of the first nMOS transistor are coupled to an input of the amplifier;
- wherein a gate of the second pMOS transistor and a gate of the second nMOS transistor are coupled to a drain of the first pMOS transistor and a drain of the first nMOS transistor;
- and
- wherein a gate of the third pMOS transistor and a gate of the third nMOS transistor are coupled to an inverse input of the amplifier.
11 more elements
An apparatus comprising:
- an amplifier;
- and
- a delay and gain circuit coupled to an output of the amplifier, wherein an output of the delay and gain circuit is fed back to the amplifier;
- wherein the amplifier includes a first, a second and a third pMOS transistor and a first, a second and a third nMOS transistor;
- wherein a gate of the first pMOS transistor and a gate of the first nMOS transistor are coupled to an input of the amplifier;
- wherein a gate of the second pMOS transistor and a gate of the second nMOS transistor are coupled to a drain of the first pMOS transistor and a drain of the first nMOS transistor;
- and
- wherein a gate of the third pMOS transistor and a gate of the third nMOS transistor are coupled to an inverse input of the amplifier.
5 more elements
A system comprising:
- a transmitter;
- a receiver;
- and
- a transmission line coupled to the transmitter and the receiver;
- the receiver including:
- an amplifier;
- a first inverter having an input coupled to an output of the amplifier;
- and
- a second inverter having an input coupled to an output of the first inverter and an output, wherein the output of the second inverter is fed back to an input of the amplifier;
- wherein the amplifier provides positive feedback and the output of the second inverter is fed back to the amplifier as negative feedback;
- and
- wherein the amplifier mixes the positive feedback and the negative feedback.
9 more elements
A system comprising:
- a transmitter;
- a receiver;
- and
- a transmission line coupled to the transmitter and the receiver;
- the receiver including:
- an amplifier;
- and
- a delay and gain circuit coupled to an output of the amplifier, wherein an output of the delay and gain circuit is fed back to the amplifier;
- wherein the amplifier provides positive feedback and the output of the delay and gain circuit is fed back to the amplifier as negative feedback;
- and
- wherein the amplifier mixes the positive feedback and the negative feedback.
8 more elements
Dependencies are inferred from the claim text.