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US 7,548,109 B2Granted
Voltage converter and display device comprising a voltage converter
AssigneeHitachi Displays, Ltd.
InventorsHisayoshi Kajiwara, Norio Mamba, Toshio Miyazawa
Life of this patent
Estimating the term…
Abstract
A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.
Claims13
A voltage converter circuit for converting an input voltage and outputting a converted voltage, comprising
- first to eighth transistors and first to fifth capacitor elements,
- wherein:
- a drain and a gate of said first transistor are connected to a first terminal, and a source of said first transistor is connected to a first node;
- a drain of said second transistor is connected to said first terminal, a gate of said second transistor is connected to a second node, and a source of said second transistor is connected to said first node;
- a drain of said third transistor is connected to said first terminal, a gate of said third transistor is connected to said first node, and a source of said third transistor is connected to said second node;
- a drain of said fourth transistor is connected to said second node, a gate of said fourth transistor is connected to a third node, and a source of said fourth transistor is connected to a fourth node;
- a drain of said fifth transistor is connected to said second node, a gate of said fifth transistor is connected to a second terminal, and a source of said fifth transistor is connected to said fourth node;
- a drain of said sixth transistor is connected to said second node, a gate of said sixth transistor is connected to said fourth node, and a source of said sixth transistor is connected to said second terminal;
- a drain and a gate of said seventh transistor are connected to said second node, and a source of said seventh transistor is connected to said third node;
- a drain of said eighth transistor is connected to said second node, a gate of said eighth transistor is connected to said fourth node, and a source of said eighth transistor is connected to said third node;
- said first capacitor element is connected between a first control signal input terminal and said first node;
- said second capacitor element is connected between a second control signal input terminal and said fourth node;
- said third capacitor element is connected between a third control signal input terminal and said third node;
- said fourth capacitor element is connected between a fourth control signal input terminal and said second node;
- said fifth capacitor element is connected at least either between said second terminal and ground or between said first terminal and ground;
- and
- first to fourth control signals having different timings are input to said first to fourth control signal input terminals, respectively.
14 more elements
A voltage converter circuit for converting an input voltage and outputting a converted voltage, comprising
- first to eighth transistors and first to fifth capacitor elements,
- wherein:
- a drain and a gate of said first transistor are connected to a first terminal, and a source of said first transistor is connected to a first node;
- a drain of said second transistor is connected to said first terminal, a gate of said second transistor is connected to a second node, and a source of said second transistor is connected to said first node;
- a drain of said third transistor is connected to said first terminal, a gate of said third transistor is connected to said first node, and a source of said third transistor is connected to said second node;
- said first capacitor is connected between a first control signal input terminal and said first node;
- one or a plurality of circuit blocks are serially connected between the source of said third transistor and a second terminal, and in each said circuit block,
- a drain of said fourth transistor is connected to said second node, a gate of said fourth transistor is connected to a third node, and a source of said fourth transistor is connected to a fourth node;
- a drain of said fifth transistor is connected to said second node, a gate of said fifth transistor is connected to said second terminal, and a source of said fifth transistor is connected to said fourth node;
- a drain of said sixth transistor is connected to said second node, a gate of said sixth transistor is connected to said fourth node, and a source of said sixth transistor is connected to said second terminal;
- a drain and a gate of said seventh transistor are connected to said second node, and a source of said seventh transistor is connected to said third node;
- a drain of said eighth transistor is connected to said second node, a gate of said eighth transistor is connected to said fourth node, and a source of said eighth transistor is connected to said third node;
- said second capacitor element is connected between a second control signal input terminal and said fourth node;
- said third capacitor element is connected between a third control signal input terminal and said third node;
- said fourth capacitor element is connected between a fourth control signal input terminal and said second node,
- wherein said circuit block uses the gate of said seventh transistor as an input from a previous block and the source of said sixth transistor as an output to a next block;
- said fifth capacitor element is connected at least either between said second terminal and ground or between said first terminal and ground;
- and
- first to fourth control signals having different timings are input to said first to fourth control signal input terminals, respectively.
16 more elements
Dependencies are inferred from the claim text.