Internal read signal generator and semiconductor memory device having the same
AssigneeHynix Semiconductor Inc.
InventorSang-Sic Yoon
Life of this patent
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Abstract
The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.
Claims9
A semiconductor memory device comprising:
- a first delay means for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal;
- a signal transfer means for transferring the input signal in synchronization with the delayed clock signal of the first delay means;
- a second delay means for delaying an output signal of the signal transfer means;
- and
- an output means for combining the input signal and an output signal of the second delay means, wherein an amount of the delay of the second delay means is determined in order that an output signal of the output means has a period corresponding to that of the clock signal.
An apparatus for generating an internal read signal comprising:
- a first delay means for delaying an internal clock signal in order to obtain a margin of a setup/hold time of an internal read signal;
- a flip-flop unit to transfer an input source signal for generating the internal read signal in synchronization with the delayed clock signal of the first delay means;
- a second delay means for delaying an output signal of the flip-flop unit;
- and
- an output means for combining the input source signal and an output signal of the second delay means, wherein an amount of delay of the second delay means is determined in order that the internal read signal has a period corresponding to that of the internal clock signal.
A semiconductor memory device comprising:
- a first delay means for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal;
- a signal transfer means for transferring the input signal in synchronization with the delayed clock signal of the first delay means;
- and
- a second delay means for delaying an output signal of the signal transfer means to compensate for additional delay caused by the first delay means.
Dependencies are inferred from the claim text.