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AssigneeCosmic Circuits Private Limited
InventorsPrasenjit Bhowmik, Sundararajan Krishnan, G. Sriram
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A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.
A delay cell, the delay cell comprising:
A delay line including a sequence of delay cells, a first delay cell of the sequence being driven by a reference clock signal, and each successive delay cell of the sequence being driven by an output from a preceding delay cell, wherein each delay cell of the sequence comprises:
A method for maintaining a gain and a duty cycle of a delay cell, the delay cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, and a load capacitor, the method comprising:
Dependencies are inferred from the claim text.