Delay locked loop circuit for semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorSeok-Bo Shim
Life of this patent
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Abstract
A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides a phase of the output of the duty cycle correcting part, adjusts a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and outputs the two signals as delay locked loop clocks.
Claims20
A delay locked loop circuit for a semiconductor memory apparatus, the delay locked loop circuit comprising:
- a duty cycle correcting part configured to correct and output duty cycles of internal clocks;
- a clock pulse width detecting part configured to detect a pulse width of an external clock and output a pulse width detecting signal based thereon;
- and
- a driving part configured to divide a phase of the duty cycles output of the duty cycle correcting part, adjust a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and output the two signals as delay locked loop clocks.
A delay locked loop circuit for a semiconductor memory apparatus, the delay locked loop circuit comprising:
- a duty cycle correcting part configured to correct and output duty cycles of internal clocks;
- and
- a driving part configured to divide a phase of the duty cycles output of the duty cycle correcting part, adjust a pulse width of at least one of two signals obtained by dividing the phase, and output the two signals as delay locked loop clocks.
Dependencies are inferred from the claim text.