Delay locked loop
AssigneeHynix Semiconductor Inc.
InventorsKwang Jun Cho, Kie Bong Ku
Life of this patent
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Abstract
The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
Claims9
A digital duty cycle correction (DCC) circuit, comprising:
- a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a first capacitor, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of a delayed second clock ;
- and
- a second conversion circuit for convening the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
Dependencies are inferred from the claim text.