Isolation scheme for static and dynamic FPGA partial programming
AssigneeActel Corporation
InventorsZhigang Wang, Fethi Dhaoui, Santosh Yachareni
Life of this patent
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Abstract
An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively disposed in the first and second deep n-wells. First and second segments of Flash memory are disposed in the in first and second p-wells. N-type regions are disposed in each deep n-well between the outer boundary of the p-wells and the outer boundary of the deep n-wells.
Claims8
An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells including:
- a p-type semiconductor region;
- a first deep n-well disposed in the p-type semiconductor region and having an outer boundary;
- a second deep n-well disposed in the p-type semiconductor region and having an outer boundary, the second deep n-well separated from the first deep n-well region;
- a first p-well disposed in the first deep n-well and having an outer boundary;
- a second p-well disposed in the second deep n-well and having an outer boundary;
- a first segment of Flash memory disposed in the in first p-well;
- a second segment of Flash memory disposed in the second p-well;
- a first n-type region disposed in the first deep n-well between the outer boundary of the first p-well the outer boundary of the first deep n-well, the first n-type region having a dopant concentration higher than that of the first deep n-well;
- a second n-type region disposed in the second deep n-well between the outer boundary of the second p-well the outer boundary of the second deep n-well, the second n-type region having a dopant concentration higher than that of the second deep n-well.
Dependencies are inferred from the claim text.