Impedance control circuit in semiconductor device and impedance control method

An impedance control circuit in a semiconductor device, the circuit comprising:

• an impedance detector for generating a first detection voltage to a detection pad connected between an external determination resistor and a first group transistor array in response to an applied first control code data, and outputting a second detection voltage to a first resistance divider terminal commonly connected between a second and third group transistor array, in response to the first control code data and a second control code data;
• a terminator, which comprises a second resistance divider terminal, and a compensating unit that is connected to the second resistance divider terminal to compensate for an impedance mismatch caused by a quantization error of the first and second control code data, the second resistance divider terminal being commonly connected between a fourth and fifth group transistor array and the compensating unit, wherein the fourth and fifth group transistor array includes a plurality of pull-up transistors and a plurality of pull-down transistors, wherein each of the pull-up transistors is connected in series to a different one of the pull-down transistors, wherein the pull-up transistors are connected in parallel to one another, and wherein the pull-down transistors are connected in parallel to one another, wherein the mismatch compensating unit comprises one of a pull-up or pull-down transistor and a resistor, the resistor having a resistance value of twice a unit resistance of the fifth group transistor array such that a mismatch between pull-up and pull-down resistance in the fourth and fifth group transistor array is reduced by half a digital control resolution;
• and an impedance controller for performing a comparison on the first and second detection voltages of the impedance detector to generate the first and second control code data.

An impedance control method in a semiconductor device, comprising:

• preparing an output driver, the output driver including an impedance detector for generating a first and a second detection voltage and a mismatch compensating unit connected in parallel with a pull-down transistor array of a commonly connected pull-up and pull-down transistor array, wherein the pull-up and pull-down array includes a plurality of pull-up transistors and a plurality of pull-down transistors, wherein each of the pull-up transistors is connected in series to a different one of the pull-down transistors, wherein the pull-up transistors are connected in parallel to one another, and wherein the pull-down transistors are connected in parallel to one another;
• selecting a first code representing a resistance value less than a reference resistance value for generating a pull-up control code data, and selecting a second code representing a resistance value greater than the reference resistance value for generating a pull-down control code data, so that the first and second detection voltage of the impedance detector become approximated to a predetermined reference voltage value;
• and using the mismatch compensating unit to reduce an impedance mismatch between the resistance values wherein the mismatch compensating unit comprises one of a pull-up or pull-down transistor and a resistor, the resistor having a resistance value of twice a unit resistance of the commonly connected pull-up and pull-down transistor array such that a mismatch between pull-up and pull-down resistances of the commonly connected pull-up and pull-down transistor array is reduced by half a digital control resolution.

An impedance control method in a semiconductor device, comprising:

• preparing a terminator, the terminator including an impedance detector for generating a first and second detection voltage and a mismatch compensating unit connected in parallel with a pull-up transistor array of a commonly connected pull-up and pull-down transistor array, wherein the pull-up and pull-down array includes a plurality of pull-up transistors and a plurality of pull-down transistors, wherein each of the pull-up transistors is connected in series to a different one of the pull-down transistors, wherein the pull-up transistors are connected in parallel to one another, and wherein the pull-down transistors are connected in parallel to one another;
• selecting a first code representing a resistance value greater than a reference resistance value for generating a pull-up control code data, and selecting a second code representing a resistance value less than the reference resistance value for generating a pull-down control code data, so that the first and second detection voltages of the impedance detector become approximated to a predetermined reference voltage value;
• and using the mismatch compensating unit to reduce an impedance mismatch between the resistance values wherein the mismatch compensating unit comprises one of a pull-up or pull-down transistor and a resistor, the resistor having a resistance value of twice a unit resistance of the commonly connected pull-up and pull-down transistor array such that a mismatch between pull-up and pull-down resistances of the commonly connected pull-up and pull-down transistor array is reduced by half a digital control resolution.