Random access of user design states in a configurable IC
AssigneeTabula, Inc.
InventorsBrad Hutchings, Jason Redgrave, Steven Teig, Herman Schmit
Life of this patent
Estimating the term…
Abstract
Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC.
Claims15
An integrated circuit (“IC”) comprising:
- a plurality of configurable logic circuits;
- a first routing network for connecting the configurable logic circuits;
- a plurality of user design state (“UDS”) circuits;
- and
- a second debug network communicatively coupled to the UDS circuits, said second debug network for receiving addresses for a plurality of the UDS circuits in a random access manner and for randomly reading state values stored by the addressed UDS circuits during user-design operation of the IC;
- wherein to read the plurality of UDS circuits, a plurality of read instructions are transmitted over the second debug network of the IC.
An integrated circuit (“IC”) comprising:
- a plurality of configurable logic circuits;
- a first routing network for connecting the configurable logic circuits;
- a plurality of user design state (“UDS”) circuits;
- and
- a second debug network communicatively coupled to the UDS circuits, said second debug network for receiving addresses for a plurality of the UDS circuits in a random access manner, and for randomly writing state values to the addressed UDS circuits,
- wherein to write to the plurality of UDS circuits, a plurality of write instructions are transmitted over the second debug network of the IC.
A method of accessing an integrated circuit (“IC”) comprising a plurality of configurable circuits and a plurality of user design state (“UDS”) circuits, the method comprising:
- while the IC is performing user-design operations, randomly addressing different UDS circuits through a first network connected to the UDS circuits, said first network separate from a second routing fabric network for connecting the configurable logic circuits of the IC;
- and
- reading state values stored by the randomly addressed UDS circuits during the user-design operation of the IC;
- wherein the UDS circuits are arranged in the IC according to a particular arrangement;
- wherein randomly addressing different UDS circuits comprises successively accessing at least a plurality of the UDS circuits that are not aligned according to the particular arrangement.
A method of accessing an integrated circuit (“IC”) comprising a plurality of configurable circuits and a plurality of user design state (“UDS”) circuits, the method comprising:
- receiving, through a configuration network connected to the UDS circuits, addresses for different UDS circuits in a random access manner;
- and
- writing state values stored by the randomly addressed UDS circuits;
- wherein the UDS circuits are arranged in the IC according to a particular arrangement;
- wherein randomly addressing different UDS circuits comprises successively accessing at least a plurality of the UDS circuits that are not aligned according to the particular arrangement.
Dependencies are inferred from the claim text.