Fault tolerant integrated circuit architecture

An apparatus comprising:

• a state machine element;
• an interconnect element;
• an intercluster queue coupled to the interconnect element, the intercluster queue to buffer a data word from a first plurality of composite circuit elements and to transfer the data word to an adjacent second plurality of composite circuit elements;
• the first plurality of composite circuit elements coupled to the interconnect element, each composite circuit element comprising a uniform element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the first plurality of composite circuit elements having a first action, a second composite circuit element of the first plurality of composite circuit elements having a second action, the first composite circuit element having an assignable first data link to the second composite circuit element through the interconnect element, wherein each uniform element interface comprises:
• a first memory coupled to the corresponding circuit element, and when the corresponding circuit element is configurable, the first memory to store at least one configuration of the corresponding circuit element;
• an element controller coupled to the corresponding circuit element;
• a second memory coupled to the corresponding circuit element, the second memory to provide a plurality of input queues for data input to the corresponding circuit element;
• and
• a third memory coupled to the corresponding circuit element, the third memory to provide a plurality of output queues for data output from the corresponding circuit element.

An apparatus comprising:

• a plurality of circuit arrays, each circuit array of the plurality of circuit arrays comprising:
• an interconnect element;
• a plurality of communication elements coupled to the interconnect element, the plurality of communication elements to transfer data from a first circuit array to a second circuit array of the plurality of circuit arrays;
• a plurality of composite circuit elements coupled to the interconnect element, each composite circuit element comprising an element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the plurality of composite circuit elements having a first action, a second composite circuit element of the plurality of composite circuit elements having a second action, the first composite circuit element having a first data link to the second composite circuit element through the interconnect element;
• and
• a state machine element coupled to the plurality of composite circuit elements.

An integrated circuit comprising:

• a first plurality of composite circuit elements, a first composite circuit element of the first plurality of composite circuit elements to perform a first function;
• a plurality of communication elements coupled to the first plurality of composite circuit elements;
• an interconnect element coupled to the first plurality of composite circuit elements, the interconnect element to couple any output queue of a composite circuit element of the first plurality of composite circuit elements to any input queue of another composite circuit element of the first plurality of composite circuit elements or to a communication element of the plurality of communication elements;
• a state machine element coupled to the first plurality of composite circuit elements;
• and
• a second plurality of composite circuit elements having a plurality of data links to the first plurality of composite circuit elements through at least one communication element of the plurality of communication elements for performance of the first function.

An integrated circuit comprising:

• a first plurality of composite circuit elements, a first composite circuit element of the first plurality of composite circuit elements to perform a first function;
• a memory coupled to the first plurality of composite circuit elements;
• a plurality of communication elements coupled to the first plurality of composite circuit elements;
• an interconnect element coupled to the first plurality of composite circuit elements, the interconnect element to couple any output queue of a composite circuit element of the first plurality of composite circuit elements to any input queue of another composite circuit element of the first plurality of composite circuit elements or to a communication element of the plurality of communication elements;
• a state machine element coupled to the first plurality of composite circuit elements;
• and
• a second plurality of composite circuit elements having a plurality of data links to the first plurality of composite circuit elements through at least one communication element of the plurality of communication elements for performance of the first function.