Pulse width modulated buck voltage regulator with stable feedback control loop

A voltage regulator comprising:

• a comparator adapted to compare an output voltage of the voltage regulator with a reference voltage;
• a counter configured to be set in a count-down mode if the output voltage raises above the reference voltage, and to be set in a count-up mode if the output voltage falls below the reference voltage;
• wherein said counter's count is decremented with each transition of a clock signal if said counter is set in the count-down mode and wherein said counter's count is incremented with each transition of the clock signal if said counter is set in the count-up mode;
• and
• a control circuit configured to receive the counter's count and to change, in accordance therewith, a duty cycle of a first signal to which the output voltage is responsive, wherein said clock signal has a frequency that is 1/N times a frequency of the first signal;
• wherein the control circuit comprises a duty cycle converter configured to vary one of charging time and discharging time of a capacitor in response to the counter's count, and the duty cycle converter comprises M legs, each leg adapted to supply a current to the capacitor when a first switch disposed in that leg is selected to be closed, each leg further adapted to sink a current from the capacitor when a second switch disposed in that leg is selected to be closed, wherein said first and second switches in each leg are adapted so as not to be closed concurrently.

A method of regulating an output voltage, the method comprising:

• decrementing a count with each transition of a clock signal if the output voltage is above a first reference voltage;
• incrementing the count with each transition of the clock signal if the output voltage is below a second reference voltage;
• maintaining the count if the output voltage falls between the first and second reference voltages;
• varying one of charging time and discharging time of a capacitor in response to the count;
• supplying a current that is S1 times a reference charging current to said capacitor via at least one of M legs during a first time period so as to decrease the charging time of the capacitor;
• sinking a current that is S2 times a reference discharging current from said capacitor via at least one of the M legs during a second time period so as to decrease the discharging time of the capacitor;
• and
• changing a duty cycle of a first signal in accordance with the count, wherein said output voltage is generated in response to the first signal, and wherein said clock signal has a frequency that is 1/N times a frequency of the first signal, wherein N is greater than 1;
• wherein said first and second time periods do not overlap.

A method of regulating an output voltage, the method comprising:

• decrementing a count with each transition of a clock signal if the output voltage is above a reference voltage;
• incrementing the count with each transition of the clock signal if the output voltage is below the reference voltage;
• varying one of charging time and discharging time of a capacitor in response to the count;
• supplying a current that is S1 times a reference charging current to said capacitor via at least one of M legs during a first time period so as to decrease the charging time of the capacitor;
• sinking a current that is S2 times a reference discharging current from said capacitor via at least one of the M legs during a second time period so as to decrease the discharging time of the capacitor;
• and
• changing a duty cycle of a first signal in accordance with the count, wherein said output voltage is generated in response to the first signal, wherein said clock signal has a frequency that is 1/N times a frequency of the first signal, and wherein N is greater than one;
• wherein said first and second time periods do not overlap.