Semiconductor chip having bond pads

A semiconductor chip having one or more peripheral bond pads, the semiconductor chip comprising:

• a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other;
• a bond pad-wiring pattern formed on at least a part of the peripheral circuit region of the semiconductor substrate;
• a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate, the passivation layer having an opening filled with a conductive material;
• a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern through the conductive material filled in the opening;
• and
• an insulating layer formed over the pad-rearrangement pattern, the insulating layer having an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad, the bond pad disposed over at least a part of the cell region.