SRAM cell
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Edward J. Nowak
Life of this patent
Estimating the term…
Abstract
Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise non-planar partially depleted three-gated FETs having a greater channel width and a greater gate length and, thus, a greater drive current relative to the pass-gate and pull-up FETs. Additionally, for optimal electron mobility and hole mobility, respectively, the channels of the n-FETs and p-FETs can comprise semiconductors with different crystalline orientations.
Claims17
A memory cell comprising:
- a first non-planar transistor comprising:
- a first semiconductor fin comprising a first channel;
- and
- first gates adjacent said first channel;
- a second non-planar transistor comprising:
- a second semiconductor fin comprising a second channel;
- and
- second gates adjacent said second channel;
- and
- a third non-planar transistor comprising:
- a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls;
- and
- third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
- wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
- wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
- wherein said third semiconductor fin is wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
A memory cell comprising:
- a non-planar pass-gate transistor comprising:
- a first semiconductor fin comprising a first channel;
- and
- first gates adjacent said first channel;
- a non-planar pull-up transistor comprising:
- a second semiconductor fin comprising a second channel;
- and
- second gates adjacent said second channel;
- and
- a non-planar pull-down transistor comprising:
- a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls;
- and
- third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
- wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
- wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
- wherein third semiconductor fin is wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
A memory cell comprising:
- a non-planar pass-gate transistor comprising:
- a first semiconductor fin comprising a first channel;
- and
- first gates adjacent said first channel;
- a non-planar pull-up transistor comprising:
- a second semiconductor fin comprising a second channel;
- and
- second gates adjacent said second channel;
- and
- a non-planar pull-down transistor comprising:
- a third semiconductor fin comprising a third channel, having a top surface and opposing sidewalls;
- and
- third gates adjacent said top surface and said opposing sidewalls, said third gates being longer than said first gates and said second gates,
- wherein said first semiconductor fin, said second semiconductor fin and said third semiconductor fin each have approximately equal heights,
- wherein said first semiconductor fin and said second semiconductor fin each have approximately equal widths such that said first channel and said second channel are fully depleted, and
- wherein third semiconductor fin is at least 1.5 times wider than said first semiconductor fin and said second semiconductor fin such that said third channel is only partially depleted.
Dependencies are inferred from the claim text.