MOS semiconductor device with low ON resistance
AssigneeNEC Electronics Corporation
InventorMasaji Nakano
Life of this patent
Estimating the term…
Abstract
The semiconductor device 1 includes transistors 10, 20. Each of the transistors 10 (first transistor) is a MOSFET, and includes source regions 102, 106, a drain region 104, and a gate electrode 110. Each of the transistors 20 (second transistor) is also a MOSFET, and includes source regions 202, 206, a drain region 204, and a gate electrode 210. The source region 106 of the transistor 10 and the source region 202 of the transistor 20 are the identical region in the semiconductor substrate 90. In other words, the source region 106 and the source region 202 are shared by the both transistors.
Claims6
A semiconductor device comprising a plurality of first transistors and a plurality of second transistors;
- each of said plurality of first transistors including a first source/drain region, a second source/drain region located opposite to said first source/drain region across a first gate region, a third source/drain region located opposite to said second source/drain region across a second gate region and electrically connected to said first source/drain region, and a first gate electrode provided in each of said first and second gate regions;
- and
- each of said plurality of second transistors including said third source/drain region, a fourth source/drain region located opposite to said third source/drain region across a third gate region, a fifth source/drain region located opposite to said fourth source/drain region across a fourth gate region and electrically connected to said first and third source/drain regions, and a second gate electrode provided in each of said third and fourth gate regions, and
- means for controlling said second gate electrode independently of said first gate electrode;
- wherein said first and second transistors are alternately arranged;
- and
- said first source/drain region of said first transistor and said fifth source/drain region of said second transistor adjacent to said first transistor on the side of said first source/drain region are shared by said first and second transistors.
A semiconductor device comprising:
- a first transistor including a first source/drain region, a second source/drain region located opposite to said first source/drain region across a first gate region, a third source/drain region located opposite to said second source/drain region across a second gate region and electrically connected to said first source/drain region, and a first gate electrode provided in each of said first and second gate regions;
- and
- a second transistor including said third source/drain region, a fourth source/drain region located opposite to said third source/drain region across a third gate region, a fifth source/drain region located opposite to said fourth source/drain region across a fourth gate region and electrically connected to said first and third source/drain regions, and a second gate electrode provided in each of said third and fourth gate regions, and
- means for controlling said second gate electrode independently of said first gate electrode
- a first source/drain interconnect extending along an alignment direction of said first and second transistors, and electrically connected to said second source/drain region;
- a second source/drain interconnect adjacent to said first source/drain interconnect, extending along said alignment direction, and electrically connected to said fourth source/drain region;
- a third source/drain interconnect adjacent to said first source/drain interconnect on the opposite side to said second source/drain interconnect, extending along said alignment direction, and electrically connected to said first, third and fifth source/drain regions;
- and
- a fourth source/drain interconnect adjacent to said second source/drain interconnect on the opposite side to said first source/drain interconnect, extending along said alignment direction, and electrically connected to said first, third and fifth source/drain regions.
Dependencies are inferred from the claim text.