Transistor devices, transistor structures and semiconductor constructions
AssigneeMicron Technology, Inc.
InventorsSanh D. Tang, Gordon Haller, Kris K. Brown, Tuman Earl Allen, III
Life of this patent
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Abstract
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
Claims41
A transistor device, comprising:
- a semiconductor substrate;
- and
- a gate extending within the semiconductor substrate, a gate dielectric over the gate, a pair of source/drain regions on opposite sides of the gate, and a channel region within the semiconductor substrate, at least a portion of the channel region defining the lowermost structure of the transistor device;
- and
- wherein the gate encircles a portion of the semiconductor substrate.
A transistor device, comprising:
- a semiconductor substrate comprising an upper surface;
- a pair of source/drain regions comprising portions of the semiconductor substrate;
- a channel region comprising at least three laterally-spaced portions within the semiconductor substrate and each of the three portions extending generally perpendicularly relative to the upper surface of the semiconductor substrate;
- and
- a gate portion disposed between the pair of the source/drain regions, wherein one of the pair of the source/drain regions extends substantially vertically and defines the elevationally uppermost structure of the transistor device.
A semiconductor construction, comprising:
- a conductive post extending upward from an upper surface of a semiconductor substrate, the conductive post comprising a circular cross section;
- a source/drain region below the conductive post within the semiconductor substrate and electrically coupled with the conductive post;
- a transistor channel extending below the source/drain region and comprising at least one curved portion of the semiconductor substrate;
- and
- a gate within the semiconductor substrate adjacent the transistor channel, wherein the gate surrounds the source/drain region.
A vertical transistor structure, comprising:
- a silicon substrate;
- a channel region defined within the silicon substrate and extending generally vertically relative the silicon substrate;
- a first source/drain region elevationally above the channel region;
- a gate laterally adjacent the channel region within the silicon substrate, at least a portion of the channel region being elevationally below an entirety of the gate;
- a second source/drain region operatively proximate the gate;
- a third source/drain region operatively proximate the gate;
- and
- wherein the gate surrounds another portion of the channel region.
A transistor device, comprising:
- a semiconductor substrate;
- a gate extending within the semiconductor substrate, a gate dielectric over the gate, a pair of source/drain regions on opposite sides of the gate, and a channel region within the semiconductor substrate, at least a portion of the channel region defining the lowermost structure of the transistor device;
- and
- wherein the gate surrounds another portion of the channel region.
A vertical transistor structure, comprising:
- a silicon substrate;
- a channel region defined within the silicon substrate and extending generally vertically relative the silicon substrate;
- a first source/drain region elevationally above the channel region;
- a gate laterally adjacent the channel region within the silicon substrate, at least a portion of the channel region being elevationally below an entirety of the gate;
- a second source/drain region operatively proximate the gate;
- a third source/drain region operatively proximate the gate;
- and
- wherein the gate surrounds the first source/drain region.
Dependencies are inferred from the claim text.