Scalable electrically eraseable and programmable memory (EEPROM) cell array

A memory system comprising:

• a first non-volatile memory cell having a first access transistor and a first non-volatile memory transistor, wherein the first access transistor has a drain region that is continuous with a source region of the first non-volatile memory transistor;
• a second non-volatile memory cell having a second access transistor and a second non-volatile memory transistor, wherein the second access transistor has a drain region that is continuous with a source region of the second non-volatile memory transistor, wherein the first and second access transistors share a common source region, and wherein the first and second non-volatile memory cells are located in a first well region having a first conductivity type, and wherein the first well region is located in a second well region having a second conductivity type, opposite the first conductivity type, and wherein the first and second access transistors comprise control gates fabricated from a first polysilicon layer and wherein the first and second non-volatile memory transistors comprise floating gates fabricated from the first polysilicon layer;
• and
• a first bit line connected to a drain of the first non-volatile memory transistor and a drain of the second non-volatile memory transistor.