Semiconductor memory device and method for manufacturing the same

A semiconductor memory device, comprising:

• a first word-line;
• a first non-inverted bit-line;
• a first inverted bit-line;
• a first global interconnection layer;
• a first memory capacitor that is comprised of a first storage electrode, a first counter electrode, and a first oxide dielectric film formed between the first storage electrode and the first counter electrode;
• a second memory capacitor that is comprised of a second storage electrode, a second counter electrode, and a second oxide dielectric film formed between the second storage electrode and the second counter electrode;
• a first local interconnection layer that is electrically conductive and permeable to hydrogen, the first local interconnection layer including a first contact portion that has a contact with the first counter electrode and is separated from the first oxide dielectric film through the first counter electrode, a second contact portion that has a contact with the second counter electrode and is separated from the second oxide dielectric film through the second counter electrode, and a first non-contact portion that connects the first contact portion and the second contact portion and is separated from the first memory capacitor and the second memory capacitor;
• a first hydrogen barrier layer that is electrically insulating and impermeable to hydrogen, the first hydrogen barrier layer covering at least the first contact portion and the second contact portion of the first local interconnection layer;
• a first switching transistor that has a first gate electrode electrically connected to the first word-line, the first switching transistor electrically connecting the first non-inverted bit-line and the first storage electrode;
• a second switching transistor that has a second gate electrode electrically connected to the first word-line, the second switching transistor electrically connecting the first inverted bit-line and the second storage electrode;
• and
• a third switching transistor that has a third gate electrode electrically connected to the first word-line, the third switching transistor electrically connecting the first local interconnection layer and the first global interconnection layer.