Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates

A method of forming an integrated semiconductor circuit, the method comprising:

• providing a semiconductor substrate that is formed from a monocrystalline semiconductor material;
• subjecting the semiconductor material to thermal nitridation so as to form a stress relief layer on a process surface of the semiconductor substrate;
• applying a protective layer portion of a mask to the stress relief layer, wherein the protective layer portion is made from a covering material with an expansion coefficient that is significantly different from that of the semiconductor material;
• applying a hard-mask portion of the mask to the protective layer portion;
• and
• patterning the mask via a photolithographic method, the pattern of the mask being imaged into the semiconductor substrate so as to form a trench structure in the semiconductor substrate,
• wherein the hard-mask portion is recessed by a wet etching process and an undercut is prevented from forming within the stress relief layer.

A method of applying a covering layer to a semiconductor substrate, comprising:

• providing a semiconductor substrate that is formed from a monocrystalline semiconductor material;
• subjecting the semiconductor material to thermal nitridation so as to form a stress relief layer on a process surface of the semiconductor substrate, wherein the nitridation includes orienting the semiconductor substrate within a process chamber and subjecting the semiconductor substrate to a heat treatment to cause oxygen to substantially diffuse out of the semiconductor substrate at least down to a target depth defined by a lower edge of structures that are to be formed in the semiconductor substrate, and the nitridation is carried out at least during a portion of the heat treatment;
• applying a covering layer to the stress relief layer, wherein the covering layer is made from a covering material with an expansion coefficient that is significantly different from that of the semiconductor material;
• and
• forming a trench in the semiconductor substrate.

A method of forming a layer arrangement, the method comprising:

• providing a semiconductor substrate comprising a monocrystalline semiconductor material;
• arranging a covering layer in portions over a process surface of the semiconductor substrate, the covering layer having a layer thickness of at least 50 nanometers and comprising a covering material with a coefficient of thermal expansion that is significantly different from that of the semiconductor material;
• and
• providing a stress relief layer between the semiconductor substrate and the covering layer, the stress relief layer being suitable for preventing the covering layer from flaking off in the event of high thermal loading, consisting of a thermally produced semiconductor nitride and having a layer thickness of no greater than 2.5 nanometers.