Method for stacking semiconductor chips

A semiconductor apparatus comprising:

• a first semiconductor chip having a first edge to a first side, a first surface and a second surface, the first surface including first contact pads near the first edge and active components remote from the first edge;
• first vias contiguous with the first edge, the vias having a diameter, an insulating coat and a metal-filled core, the core at least partially exposed along the first side;
• each first via having on the first surface a routing trace to one first pad;
• seals against microcracks and thermo-mechanical stress located between the first vias and the active components of the first chip;
• a second semiconductor chip having a second edge to a second side, a third surface and a fourth surface, the third surface including second contact pads near the second edge and active components remote from the second edge;
• second vias contiguous with the second edge, the vias in locations matching the locations of the first vias at the first edge, the core at least partially exposed along the second side;
• each second via having on the third surface a routing trace to one second pad;
• seals against microcracks and thermo-mechanical stress, the seals located between the second vias and the active components of the second chip;
• and
• the second side attached to the first side so that each second via is aligned and in electrical contact with the respective first via, whereby the first and the second chip form a horizontal chain.

A method for fabricating a semiconductor apparatus comprising the steps of:

• providing a semiconductor wafer having a first and a second surface, the first surface including a plurality of chips separated by scribe streets;
• each chip having on the first surface active components remote from the scribe streets, first contact pads near the scribe streets, and vias between the first pads and the scribe streets, the vias having a diameter, an insulating coat, a metal-filled core and, on the first surface, a routing trace to one pad;
• each chip further having seals against microcracks located between the vias and the respective nearest scribe street, and seals against thermo-mechanical stress located between the vias and the active components;
• singulating the chips from the wafer along the scribe streets;
• attaching a metal bump to the second surface of each via;
• providing a plurality of workpieces having a third surface including second contact pads matching the locations of the vias;
• stacking each chip vertically on a workpiece so that the second surface faces the third surface and each via bump is aligned and in electrical contact with the respective second contact pad;
• and
• attaching the bumps to the second pads metallurgically.

A method for fabricating a semiconductor apparatus comprising the steps of:

• providing a first semiconductor wafer having a first and a second surface, the first surface including a plurality of chips separated by scribe streets;
• each chip having on the first surface contact pads near the scribe streets, and active components remote from the scribe streets;
• first vias having a diameter, an insulating coat, a metal-filled core, and on the first surface a routing trace to one pad;
• at least a portion of the first vias contiguous with at least a first scribe street;
• each chip having seals against thermo-mechanical stress located between the first vias and the active components;
• singulating the chips from the first wafer along the scribe streets, thereby at least partially exposing the metal cores of the first vias contiguous with the at least one scribe street;
• providing a second semiconductor wafer having a third and a fourth surface, the third surface including a plurality of chips separated by scribe streets;
• each chip having on the third surface contact pads near the scribe streets, and active components remote from the scribe streets;
• further second vias having a diameter, an insulating coat, a metal-filled core and, on the third surface, a routing trace to one pad, at least a portion of the second vias contiguous with at least a second scribe street in locations matching the locations of the first vias contiguous with the first scribe street;
• each chip further having seals against thermo-mechanical stress located between the second vias and the active components;
• singulating the chips from the second wafer along the scribe streets, thereby at least partially exposing the metal cores of the second vias contiguous with the at least one scribe street;
• orienting a chip from the second wafer and a chip from the first wafer so that the exposed metal cores of the second vias are aligned with the respective exposed metal cores of the first vias;
• attaching and electrically connecting the respective metal cores to form a horizontal chain of the chips.