Microelectronic device and a method for its manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChien-Chao Huang
Life of this patent
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Abstract
Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of the semiconductor substrate layer. A semiconductor layer is then formed in the openings directly upon the exposed portions of the semiconductor substrate layer using a second material different from the first material (e.g., silicon germanium or silicon). In other examples, multiple semiconductor layers may be formed using alternating materials.
Claims33
A method of manufacturing a shallow trench isolation structure, comprising:
- providing a semiconductor substrate layer having a first crystal material;
- forming an insulating oxide layer on the semiconductor substrate layer;
- etching the insulating oxide layer to provide a plurality of openings exposing portions of a surface of the semiconductor substrate layer, thereby to form from the insulating oxide layer patterned insulation structures that are separated by the openings;
- and
- forming at least one semiconductor layer only within the openings upon the exposed portions of the semiconductor substrate layer and between and in contact with the patterned insulation structures using a selective epitaxial growth (SEG) process, wherein the at least one semiconductor layer includes a second crystal material different from the first crystal material.
A method of manufacturing a shallow trench isolation structure, comprising:
- providing a semiconductor substrate layer that includes a first crystal material;
- forming an insulating layer on the semiconductor substrate layer;
- etching the insulating layer to form a plurality of openings exposing portions of the surface of the semiconductor substrate layer, thereby to form from the insulating layer patterned insulation structures that are separated by the openings;
- and
- forming a semiconductor island only within each of the openings of the insulating layer and between and in contact with the patterned insulation structures using a selective epitaxy growth (SEG) process, wherein at least one semiconductor island is in direct contact with the surface of the semiconductor substrate layer and a sidewall of a corresponding one of the openings,
- wherein at least one semiconductor island comprises a second crystal material different than the first crystal material.
A method of manufacturing a shallow trench isolation structure, comprising:
- forming an insulating layer on a semiconductor substrate;
- etching the insulating layer to form a plurality of openings exposing portions of the surface of the semiconductor substrate, thereby to form from the insulating layer patterned insulation structures that are separated by the openings;
- forming a first crystal layer of a first semiconductor material within each of the openings of the insulating layer and between and in contact with the patterned insulation structures using a selective epitaxy growth (SEG) process;
- and
- forming a second crystal layer of a second semiconductor material directly on the first crystal layer and only within each of the openings in the insulating layer and laterally adjacent the insulating layer, wherein the second semiconductor material is different from the first semiconductor material.
A method of manufacturing a shallow trench isolation structure, comprising:
- providing first layer on a substrate, wherein the first layer comprises a crystal material comprising at least one of germanium and carbon;
- forming an insulating layer on the first layer, wherein the insulating layer comprises silicon dioxide;
- etching the insulating layer to provide a plurality of openings exposing portions of a surface of the first layer, thereby to form from the insulating layer patterned insulation structures that are separated by the openings;
- forming a second layer directly on the first layer and only within the openings in the insulating layer and laterally adjacent the insulating layer and between and in contact with the patterned insulation structures, including forming a crystal silicon layer using a selective epitaxial growth (SEG) process in which a hydrochloride gas flow ranges between about 15 standard cubic centimeters per minute (seem) and about 200 sccm, a dichlorosilane gas flow ranges between about 10 sccm and about 300 sccm, and a processing temperature ranges between about 500° C. and about 1100° C.;
- and
- forming a third layer directly on the second layer and within the openings in the insulating layer, wherein the third layer comprises a semiconductor material.
Dependencies are inferred from the claim text.